US6529988B1
Expired / Lapsed
US
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Method and apparatus for compression of universal serial bus data transmission
Assignee: Panasonic Holdings Corp
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Filing: 1999-10-28
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Granted: 2003-03-04
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Expires: 2019-10-28
Abstract
Abstract Disclosed is an apparatus and method for transferring data from a directly from peripheral computer device to a computer via a universal serial bus. The disclosed method and apparatus can also compress the transferred data. The apparatus can include a Serial Interface Engine (SIE) connected with the computer and having a latch and a First-In-First-Out memory (FIFO) connected to the latch of the SIE. The FIFO temporarily stores data from the peripheral computer device and transfers the data to the latch of the SIE. A read input of the latch is driven at a first clock frequency and an output of the FIFO is driven at a second clock frequency. The second clock frequency is at least intermittently higher than the first clock frequency. Thus, a portion of the data placed on the output of the FIFO at the second clock frequency is not read into the latch. This allows data to be compressed as it is transferred from the FIFO to the SIE.
Inventors
- 👤 Hiroto Yoshikawa
- 👤 Masakazu Urade
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:56
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
147 words
An apparatus for transferring data from a first information processing device to a second information processing device via a universal serial bus (USB), the apparatus comprising: a serial interface engine (SIE) interconnected for communication with the second information processing device, the SIE for transferring data from the first information processing device to the second information processing device; a data output interconnected with the first information processing device and for outputting data at a given clock frequency; a latch interconnected with the SIE and directly interconnected with the data output of the first information processing device, the latch for reading data transferred from the data output of the first information processing device into the SIE at a given clock frequency; at least one clock generator for driving the latch such that data is transferred directly from the data output of the first information processing device to the SIE.
Claim 2
Independent Claim
147 words
An apparatus for transferring data from a first information processing device to a second information processing device via a universal serial bus (USB), the apparatus comprising: a serial interface engine (SIE) interconnected for communication with the second information processing device, the SIE for transferring data from the first information processing device to the second information processing device; a data output interconnected with the first information processing device and for outputting data at a given clock frequency; a latch interconnected with the SIE and directly interconnected with the data output of the first information processing device, the latch for reading data transferred from the data output of the first information processing device into the SIE at a given clock frequency; at least one clock generator for driving the latch such that data is transferred directly from the data output of the first information processing device to the SIE.
Claim 3
Dependent Claim
59 words
The apparatus of claim 1 wherein the data output interconnected with the first information processing device includes a first-in-first-out memory (FIFO) for storing and transferring data from the first information processing device to the SIE, and the at least one clock generator drives both the latch and the FIFO to transfer data directly from the FIFO to the latch.
Claim 4
Dependent Claim
48 words
The apparatus of claim 2 further including a frequency multiplier interconnected with the FIFO and the clock generator such that the FIFO is clocked at a higher frequency that the latch and data is transmitted from the FIFO at a higher rate than is read by the latch.
Claim 5
Independent Claim
186 words
An apparatus for compressing data transferred from a first information processing device to a second information processing device via a universal serial bus (USB), the apparatus comprising: a serial interface engine (SIE) for communication with the second information processing device and for transferring data from the first information processing device to the second information processing device; a first-in-first-out memory (FIFO) interconnected for communication with the SIE and for storing and transferring data from the first information processing device to the SIE, the FIFO including a data output for outputting data at a given clock frequency; a latch interconnected with the SIE and the FIFO, the latch for reading data transferred from the FIFO into the SIE at a given clock frequency; a first clock generator which drives the latch at a first frequency a second clock generator which at least intermittently drives the data output of the FIFO at a second frequency which is higher than the first frequency such that when the FIFO is driven at the second frequency, data is transmitted from the FIFO at a higher rate than is read by the latch.
Claim 6
Independent Claim
186 words
An apparatus for compressing data transferred from a first information processing device to a second information processing device via a universal serial bus (USB), the apparatus comprising: a serial interface engine (SIE) for communication with the second information processing device and for transferring data from the first information processing device to the second information processing device; a first-in-first-out memory (FIFO) interconnected for communication with the SIE and for storing and transferring data from the first information processing device to the SIE, the FIFO including a data output for outputting data at a given clock frequency; a latch interconnected with the SIE and the FIFO, the latch for reading data transferred from the FIFO into the SIE at a given clock frequency; a first clock generator which drives the latch at a first frequency a second clock generator which at least intermittently drives the data output of the FIFO at a second frequency which is higher than the first frequency such that when the FIFO is driven at the second frequency, data is transmitted from the FIFO at a higher rate than is read by the latch.
Claim 7
Dependent Claim
18 words
The apparatus of claim 4 wherein the second clock generator continuously drives the FIFO at the second frequency.
Claim 8
Dependent Claim
17 words
The apparatus of claim 5 wherein the second frequency is an integer multiple of the first frequency.
Claim 9
Dependent Claim
15 words
The apparatus of claim 6 wherein the second frequency is approximately twice the first frequency.
Claim 10
Dependent Claim
31 words
The apparatus of claim 7 wherein the second clock generator is a circuit that multiplies a first clock signal produced by the first clock generator by a factor of approximately two.
Claim 11
Dependent Claim
50 words
The apparatus of claim 4 wherein: the FIFO is driven at the second frequency only intermittently; and the first information processing device includes a buffer between the FIFO and the latch which blocks data transmission from the FIFO to the latch when the FIFO is driven at the second frequency.
Claim 12
Dependent Claim
25 words
The apparatus of claim 4 wherein the first information processing device is a computer peripheral device and the second information processing device is a computer.
Claim 13
Independent Claim
194 words
An apparatus for compressing data transferred from a first information processing device to a second information processing device via a Universal Serial Bus (USB), the apparatus comprising: a Serial Interface Engine (SIE) for communication with the second information processing device and for transferring data from the first information processing device to the second information processing device; a First-In-First-Out (FIFO) memory attached to the SIE and for storing and transferring data from the first information processing device to the SIE; a latch interconnected with the SIE and the FIFO, the latch including an input which reads the data transferred from the FIFO into the SIE; a first clock generator which drives the input of the latch at a first frequency a second clock generator which intermittently drives the FIFO at a second frequency which is different from the first frequency such that when the FIFO is driven at the second frequency, data is transmitted from the FIFO at a different rate than is read by the latch; and a buffer between the FIFO and the latch which blocks data transmission from the FIFO to the latch when the FIFO is driven at the second frequency.
Claim 14
Independent Claim
194 words
An apparatus for compressing data transferred from a first information processing device to a second information processing device via a Universal Serial Bus (USB), the apparatus comprising: a Serial Interface Engine (SIE) for communication with the second information processing device and for transferring data from the first information processing device to the second information processing device; a First-In-First-Out (FIFO) memory attached to the SIE and for storing and transferring data from the first information processing device to the SIE; a latch interconnected with the SIE and the FIFO, the latch including an input which reads the data transferred from the FIFO into the SIE; a first clock generator which drives the input of the latch at a first frequency a second clock generator which intermittently drives the FIFO at a second frequency which is different from the first frequency such that when the FIFO is driven at the second frequency, data is transmitted from the FIFO at a different rate than is read by the latch; and a buffer between the FIFO and the latch which blocks data transmission from the FIFO to the latch when the FIFO is driven at the second frequency.
Claim 15
Dependent Claim
15 words
The apparatus of claim 11 wherein the second frequency is higher than the first frequency.
Claim 16
Independent Claim
107 words
A method of compressing data transferred from a first information processing device to a second information processing device via a universal serial bus (USB) comprising: temporarily storing data generated by a first information processing device in a first-in-first-out memory (FIFO) which includes a read output; reading portions of the data from the read output of the FIFO into an input of a latch of a serial interface engine (SIE) which is for transferring the portions of the data to the second information processing device; driving the input of the latch and FIFO at a first clock frequency to transfer data directly from the FIFO to the latch.
Claim 17
Independent Claim
107 words
A method of compressing data transferred from a first information processing device to a second information processing device via a universal serial bus (USB) comprising: temporarily storing data generated by a first information processing device in a first-in-first-out memory (FIFO) which includes a read output; reading portions of the data from the read output of the FIFO into an input of a latch of a serial interface engine (SIE) which is for transferring the portions of the data to the second information processing device; driving the input of the latch and FIFO at a first clock frequency to transfer data directly from the FIFO to the latch.
Claim 18
Independent Claim
119 words
A method of compressing data transferred from a first information processing device to a second information processing device via a universal serial bus (USB) comprising: temporarily storing data generated by a first information processing device in a first-in-first-out memory (FIFO) which includes a read output; reading portions of the data from the read output of the FIFO into an input of a latch of a serial interface engine (SIE) which is for transferring the portions of the data to the second information processing device; driving the input of the latch at a first clock frequency; and at least intermittently driving the data output of the FIFO at a second clock frequency which is different from the first clock frequency.
Claim 19
Independent Claim
119 words
A method of compressing data transferred from a first information processing device to a second information processing device via a universal serial bus (USB) comprising: temporarily storing data generated by a first information processing device in a first-in-first-out memory (FIFO) which includes a read output; reading portions of the data from the read output of the FIFO into an input of a latch of a serial interface engine (SIE) which is for transferring the portions of the data to the second information processing device; driving the input of the latch at a first clock frequency; and at least intermittently driving the data output of the FIFO at a second clock frequency which is different from the first clock frequency.
Claim 20
Dependent Claim
43 words
The method of claim 14 wherein the step of driving the read output of the FIFO at the second clock frequency includes continuously driving the read output of the FIFO at the second clock frequency which is higher than the first clock frequency.
Claim 21
Dependent Claim
43 words
The method of claim 15 wherein the step of driving the read output of the FIFO at the second clock frequency includes continuously driving the read output of the FIFO at the second clock frequency which is about twice the first clock frequency.
Claim 22
Dependent Claim
44 words
The method of claim 16 including the additional step of blocking transmission of data from the output of the FIFO to the input of the latch during a period of time in which the second clock frequency is higher than the first clock frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-03 | 2006-09-02 | 2007-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-03 | 2010-09-02 | 2011-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-03 | 2014-09-02 | 2015-03-04 | $7700.00 | Window Closed / Lapsed |