US6987700B1 — Method and system for writing data to a memory

Claim 1

Independent Claim 124 words

A method for writing data to a memory, the method comprising: generating at least one clock signal; generating at least one intermediate clock signal from the at least one clock signal using at least one clock tree buffer; delaying the at least one intermediate clock signal to form at least one data strobe signal; delaying the at least one intermediate clock signal to form at least one memory clock signal; determining a lead time that the at least one memory clock signal is ahead of a data reference signal; delaying the at least one memory clock signal by the lead time, and writing the data to the memory using the at least one data strobe signal and the at least one memory clock signal.

Claim 2

Independent Claim 124 words

A method for writing data to a memory, the method comprising: generating at least one clock signal; generating at least one intermediate clock signal from the at least one clock signal using at least one clock tree buffer; delaying the at least one intermediate clock signal to form at least one data strobe signal; delaying the at least one intermediate clock signal to form at least one memory clock signal; determining a lead time that the at least one memory clock signal is ahead of a data reference signal; delaying the at least one memory clock signal by the lead time, and writing the data to the memory using the at least one data strobe signal and the at least one memory clock signal.

Claim 3

Dependent Claim 55 words

The method of claim 1 , wherein delaying the intermediate clock signal to form the memory clock signal comprises delaying the intermediate clock signal by a multiple of a fractional period of the intermediate clock signal; and delaying the intermediate clock signal further by a fraction of the fractional period of the intermediate clock signal.

Claim 4

Dependent Claim 76 words

The method of claim 2 , wherein delaying the intermediate clock signal by a multiple of the fractional period comprises inverting the intermediate clock signal; delaying the intermediate clock signal by the fractional period to form a phase shifted intermediate clock signal; inverting the phase shifted intermediate clock signal; and selecting one of the intermediate clock signal, the inverted intermediate clock signal, the phase shifted intermediate clock signal, and the inverted phase shifted intermediate clock signal.

Claim 5

Dependent Claim 14 words

The method of claim 3 , wherein the fractional period is a quarter period.

Claim 6

Dependent Claim 55 words

The method of claim 1 , wherein delaying the intermediate clock signal to form a data strobe signal comprises delaying the intermediate clock signal by a multiple of a fractional period of the intermediate clock signal; and delaying the intermediate clock signal further by a fraction of the fractional period of the intermediate clock signal.

Claim 7

Dependent Claim 76 words

The method of claim 5 , wherein delaying the intermediate clock signal by a multiple of the fractional period comprises inverting the intermediate clock signal; delaying the intermediate clock signal by the fractional period to form a phase shifted intermediate clock signal; inverting the phase shifted intermediate clock signal; and selecting one of the intermediate clock signal, the inverted intermediate clock signal, the phase shifted intermediate clock signal, and the inverted phase shifted intermediate clock signal.

Claim 8

Dependent Claim 14 words

The method of claim 6 , wherein the fractional period is a quarter period.

Claim 9

Dependent Claim 22 words

The method of claim 6 , further including ANDing the selected signal with one of a logic one and a logic zero.

Claim 10

Dependent Claim 41 words

The method of claim 1 , further comprising delaying the data in a first data channel so that the data in the first data channel is latched into the memory at a different time than data in a second data channel.

Claim 11

Dependent Claim 70 words

The method of claim 1 , further comprising: delaying data in a first data channel so that the data in the first data channel is latched into the memory at a different time than data in a second data channel, wherein the first data channel carries the data from a controller circuit to the memory and the second data channel carries the data from the controller circuit to the memory.

Claim 12

Dependent Claim 142 words

A circuit for writing data to a memory, the circuit comprising: a clock generator to generate at least one clock signal; at least one clock tree buffer to generate at least one intermediate clock signal from the at least one clock signal; a first delay circuit to generate at least one data strobe signal from the at least one intermediate clock signal, and a second delay circuit to generate at least one memory clock signal from the at least one intermediate clock signal wherein a lead time that the at least one memory clock signal is ahead of a data reference signal is determined; the at least one memory clock signal being delayed by the lead time; and the at least one data strobe signal and the at least one memory clock signal are used to latch the data into the memory.

Claim 13

Dependent Claim 142 words

A circuit for writing data to a memory, the circuit comprising: a clock generator to generate at least one clock signal; at least one clock tree buffer to generate at least one intermediate clock signal from the at least one clock signal; a first delay circuit to generate at least one data strobe signal from the at least one intermediate clock signal, and a second delay circuit to generate at least one memory clock signal from the at least one intermediate clock signal wherein a lead time that the at least one memory clock signal is ahead of a data reference signal is determined; the at least one memory clock signal being delayed by the lead time; and the at least one data strobe signal and the at least one memory clock signal are used to latch the data into the memory.

Claim 14

Dependent Claim 56 words

The circuit of claim 11 , wherein the second delay circuit comprises a delay circuit to delay the intermediate clock signal by a multiple of a fractional period of the intermediate clock signal; and a delay circuit to delay the intermediate clock signal further by a fraction of the fractional period of the intermediate clock signal.

Claim 15

Dependent Claim 96 words

The circuit of claim 12 , wherein the delay circuit to delay the intermediate clock signal by a multiple of the fractional period comprises an inverter circuit to invert the intermediate clock signal; a delay circuit to delay the intermediate clock signal by the fractional period to form a phase shifted intermediate clock signal; an inverter circuit to invert the phase shifted intermediate clock signal; and a selecting circuit to select one of the intermediate clock signal, the inverted intermediate clock signal, the phase shifted intermediate clock signal, and the inverted phase shifted intermediate clock signal.

Claim 16

Dependent Claim 14 words

The circuit of claim 13 , wherein the fractional period is a quarter period.

Claim 17

Dependent Claim 56 words

The circuit of claim 11 , wherein the first delay circuit comprises a delay circuit to delay the intermediate clock signal by a multiple of a fractional period of the intermediate clock signal; and a delay circuit to delay the intermediate clock signal further by a fraction of the fractional period of the intermediate clock signal.

Claim 18

Dependent Claim 95 words

The circuit of claim 15 , wherein the delay circuit to the intermediate clock signal by a multiple of the fractional period comprises an inverter circuit to invert the intermediate clock signal; a delay circuit to delay the intermediate clock signal by the fractional period to form a phase shifted intermediate clock signal; an inverter circuit to invert the phase shifted intermediate clock signal; and a selecting circuit to select one of the intermediate clock signal, the inverted intermediate clock signal, the phase shifted intermediate clock signal, and the inverted phase shifted intermediate clock signal.

Claim 19

Dependent Claim 14 words

The circuit of claim 16 , wherein the fractional period is a quarter period.

Claim 20

Dependent Claim 24 words

The circuit of claim 16 further including an ANDing circuit inputting the selected signal and one of a logic one and a logic zero.

Claim 21

Dependent Claim 45 words

The circuit of claim 11 , further comprising a delay circuit to delay the data in a first data channel so that the data in the first data channel is latched into the memory at a different time than data in a second data channel.

Claim 22

Dependent Claim 88 words

The circuit of claim 11 , further comprising a controller circuit for writing data to the memory, the controller circuit comprising a first data channel to carry data from the controller circuit to the memory, a second data channel to carry data from the controller circuit to the memory, and a delay circuit to delay the data in the first data channel so that the data in the first data channel is latched into the memory at a different time than the data in the second data channel.

Claim 23

Independent Claim 86 words

A method of programming a circuit for writing data to a memory, the method comprising: determining a first lead time that a memory clock signal is ahead of a data reference signal; determining a second lead time that a data strobe signal is ahead of the data reference signal; delaying the memory clock signal by the first lead time and the data strobe signal by the second lead time; and writing the data to the memory using the data strobe signal and the memory clock signal.

Claim 24

Independent Claim 86 words

A method of programming a circuit for writing data to a memory, the method comprising: determining a first lead time that a memory clock signal is ahead of a data reference signal; determining a second lead time that a data strobe signal is ahead of the data reference signal; delaying the memory clock signal by the first lead time and the data strobe signal by the second lead time; and writing the data to the memory using the data strobe signal and the memory clock signal.

Claim 25

Dependent Claim 38 words

The method of claim 21 , wherein determining a first lead time comprises determining a multiple of a fractional period of the memory clock signal and delaying the memory clock signal by the multiple of the fractional period.

Claim 26

Independent Claim 13 words

The method of 22 , wherein the fractional period is a quarter period.

Claim 27

Independent Claim 13 words

The method of 22 , wherein the fractional period is a quarter period.

Claim 28

Independent Claim 37 words

The method of 21 , wherein determining the second lead time comprises determining a multiple of a fractional period of the data strobe signal and delaying the data strobe signal by the multiple of the fractional period.

Claim 29

Independent Claim 37 words

The method of 21 , wherein determining the second lead time comprises determining a multiple of a fractional period of the data strobe signal and delaying the data strobe signal by the multiple of the fractional period.

Claim 30

Independent Claim 13 words

The method of 24 , wherein the fractional period is a quarter period.

Claim 31

Independent Claim 13 words

The method of 24 , wherein the fractional period is a quarter period.

Claim 32

Dependent Claim 54 words

The method of claim 21 , further comprising generating a clock signal; generating an intermediate clock signal from the clock signal using a clock tree buffer; delaying the intermediate clock signal to form the data strobe signal; and writing the data to the memory using the data strobe signal and the memory clock signal.

Claim 33

Dependent Claim 19 words

The method of claim 26 , further comprising delaying the intermediate clock signal to form the memory clock signal.

Claim 34

Independent Claim 124 words

A method for writing data to a memory, the method comprising: generating a plurality phase-shifted clock signals; generating a plurality of first phase-shifted intermediate clock signals from the plurality of phase-shifted clock signals using a plurality of clock tree buffers; delaying at least one of the plurality of first phase-shifted intermediate clock signals to form a data strobe signal; delaying at least one of the plurality of first intermediate clock signals to form a memory clock signal; determining a lead time that the at least one memory clock signal is ahead of a data reference signal; delaying the at least one memory clock signal by the lead time, and writing data to the memory using the data strobe signal and the memory clock signal.

Claim 35

Independent Claim 124 words

A method for writing data to a memory, the method comprising: generating a plurality phase-shifted clock signals; generating a plurality of first phase-shifted intermediate clock signals from the plurality of phase-shifted clock signals using a plurality of clock tree buffers; delaying at least one of the plurality of first phase-shifted intermediate clock signals to form a data strobe signal; delaying at least one of the plurality of first intermediate clock signals to form a memory clock signal; determining a lead time that the at least one memory clock signal is ahead of a data reference signal; delaying the at least one memory clock signal by the lead time, and writing data to the memory using the data strobe signal and the memory clock signal.

Claim 36

Dependent Claim 66 words

The method of claim 28 , wherein delaying the plurality of first intermediate clock signals to form the memory clock signal comprises generating a plurality of second phase-shifted intermediate clock signals from the first phase-shifted intermediate clock signals; generating a third intermediate clock signal by selecting one of the second phase-shifted intermediate clock signals; delaying the third intermediate clock signals to form the memory clock signal.

Claim 37

Dependent Claim 63 words

The method of claim 29 , wherein said plurality of second intermediate clock signals comprise a first shifted phase of a fractional period of the first phase-shifted intermediate clock signal and wherein delaying the third intermediate clock signals to form the memory clock signal comprises delaying the third intermediate clock signal by a second shifted phase of fraction of the first shifted phase.

Claim 38

Dependent Claim 22 words

The method of claim 30 , wherein the first shifted phase is a quarter period of the first phase-shifted intermediate clock signal.

Claim 39

Dependent Claim 102 words

The method of claim 29 , wherein said plurality of second phase-shifted intermediate clock signals comprises a first one of the second phase-shifted intermediate clock signals from a first of the plurality of clock tree buffers; a second one of the second phase-shifted intermediate clock signals generated from inverting the first one of the second phase-shifted intermediate clock signals; a third one of the second phase-shifted intermediate clock signals from a second of the plurality clock tree buffers; and, a fourth one of the second phase-shifted intermediate clock signals generated from inverting the third one of the second phase-shifted intermediate clock signals.

Claim 40

Dependent Claim 66 words

The method of claim 28 , wherein delaying the plurality of first intermediate clock signals to form the data strobe signal comprises generating a plurality of fourth phase-shifted intermediate clock signals from the first phase-shifted intermediate clock signals; generating a fifth intermediate clock signals by selecting one of the fourth phase-shifted intermediate clock signals; delaying the fifth intermediate clock signals to form the data strobe signal.

Claim 41

Dependent Claim 63 words

The method of claim 33 , wherein said plurality of fourth intermediate clock signals comprise a third shifted phase of a fractional period of the first phase-shifted intermediate clock signal and wherein delaying the fifth intermediate clock signals to form the memory clock signal comprises delaying the fifth intermediate clock signal by a fourth shifted phase of fraction of the third shifted phase.

Claim 42

Dependent Claim 102 words

The method of claim 33 , wherein said plurality of fourth phase-shifted intermediate clock signals comprises a first one of the fourth phase-shifted intermediate clock signals from a first of the plurality of clock tree buffers; a second one of the fourth phase-shifted intermediate clock signals generated from inverting the first one of the phase-shifted second intermediate clock signal; a third one of the fourth phase-shifted intermediate clock signals from a second of the plurality clock tree buffers; and a fourth one of the fourth phase-shifted intermediate clock signals generated from inverting the third one of the phase-shifted second intermediate clock signals.

Claim 43

Dependent Claim 22 words

The method of claim 33 , further comprising ANDing the selected signal with one of a logic one and a logic zero.

Claim 44

Dependent Claim 17 words

The method of claim 28 , wherein the data strobe signal is centered in the data signals.

Claim 45

Dependent Claim 27 words

The method of claim 37 , wherein the data signals are delayed by a delayed data clock generated from one of the first phase-shifted intermediate clock signals.

Claim 46

Dependent Claim 111 words

A circuit for writing data to a memory, the circuit comprising: a clock generator to generate a plurality of phase-shifted clock signals; a plurality of clock tree buffers to generate a plurality of first intermediate clock signals from the plurality of phase-shifted clock signals; and a delay circuit to generate a data strobe signal and a memory clock signal from the first intermediate clock signals, wherein a lead time that the memory clock signal is ahead of a data reference signal is determined; the memory clock signal being delayed by the lead time, and the data strobe signal and the memory clock signal are used to latch data into the memory.

Claim 47

Dependent Claim 111 words

A circuit for writing data to a memory, the circuit comprising: a clock generator to generate a plurality of phase-shifted clock signals; a plurality of clock tree buffers to generate a plurality of first intermediate clock signals from the plurality of phase-shifted clock signals; and a delay circuit to generate a data strobe signal and a memory clock signal from the first intermediate clock signals, wherein a lead time that the memory clock signal is ahead of a data reference signal is determined; the memory clock signal being delayed by the lead time, and the data strobe signal and the memory clock signal are used to latch data into the memory.

Claim 48

Dependent Claim 68 words

The circuit of claim 39 , wherein the delay circuit comprises a first delay circuit to delay at least one of the first intermediate clock signals by a fractional period of the first intermediate clock signal; and a second delay circuit to delay the first intermediate clock signals further by a fraction of the fractional period of the intermediate clock signal; whereby the memory clock signal is generated.

Claim 49

Dependent Claim 110 words

The circuit of claim 40 , wherein the first delay circuit comprises a selecting circuit to select one of the following signals as an input to the second delay circuit: a first one of the first intermediate clock signals from a first of the plurality of clock tree buffers; a second one of the first intermediate clock signals generated from inverting the first one of the first intermediate clock signal; a third one of the first intermediate clock signals from a second of the plurality clock tree buffers; and, a fourth one of the first intermediate clock signals generated from inverting the third one of the first intermediate clock signal.

Claim 50

Dependent Claim 64 words

The circuit of claim 39 , wherein the delay circuit comprises a first delay circuit to delay the first intermediate clock signals by a fractional period of the first intermediate clock signal; and a second delay circuit to delay the first intermediate clock signals further by a fraction of the fractional period of the intermediate clock signal; whereby the data strobe signal is generated.

Claim 51

Dependent Claim 110 words

The circuit of claim 42 , wherein the first delay circuit comprises a selecting circuit to select one of the following signals as an input to the second delay circuit: a first one of the first intermediate clock signals from a first of the plurality of clock tree buffers; a second one of the first intermediate clock signals generated from inverting the first one of the first intermediate clock signal; a third one of the first intermediate clock signals from a second of the plurality clock tree buffers; and, a fourth one of the first intermediate clock signals generated from inverting the third one of the first intermediate clock signal.

Claim 52

Dependent Claim 28 words

The circuit of claim 42 , further including an ANDing circuit inputting the delayed first intermediate clock signal and one of a logic one and a logic zero.

Claim 53

Dependent Claim 29 words

The circuit of claim 39 , further comprises a data clock delay circuit for delay the data signals and the data strobe signal is centered in the data signals.

Claim 54

Dependent Claim 61 words

The method of claim 45 , wherein the data clock delay circuit comprises a plurality of secondary data clock delay circuits to delay one of the plurality of first intermediate clock signal to generate a plurality of delayed data clock signals; and a selecting circuit to select one of the plurality of delayed data clock signals to the latch the data.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2009-01-16	2009-07-18	2010-01-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2013-01-16	2013-07-18	2014-01-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2017-01-16	2017-07-18	2018-01-17	$7700.00	Window Closed / Lapsed

Method and system for writing data to a memory

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