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US7215033B2
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Wafer level stack structure for system-in-package and method thereof
Assignee: Samsung Electronics Co Ltd
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Filing: 2004-07-27
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Granted: 2007-05-08
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Expires: 2024-07-27
Abstract
Abstract A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.
Inventors
- 👤 Kang-Wook Lee
- 👤 Se-Yong Oh
- 👤 Young-hee Song
- 👤 Gu-Sung Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:53
CPC Classifications
H; H10; H10W; H10W90/00; H10W72/00; H10W20/00; H10W20/20; H10W70/00; H10W70/60; H10W70/611; H10W70/614; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W72/01; H10W72/0198; H10W72/071; H10W72/073; H10W72/07351; H10W72/07352; H10W72/20; H10W72/241; H10W72/244; H10W72/247; H10W72/248; H10W72/251; H10W72/29; H10W72/30; H10W72/321; H10W72/50; H10W72/531; H10W72/5366; H10W72/541; H10W72/5445; H10W72/5449; H10W72/59; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/921; H10W72/922; H10W72/9226; H10W72/923; H10W72/941; H10W72/944; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/20; H10W90/288; H10W90/291; H10W90/297; H10W90/701; H10W90/721; H10W90/722; H10W90/724; H10W90/731; H10W90/732; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
133 words
A wafer level stack structure, comprising: a first wafer including at least one first device chip, wherein each first device chip includes a first device region, a first peripheral region surrounding the first device region, and a first plurality of input/output (I/O) pads formed in the first device region; a second wafer including at least one second device chip approximately equal in size to the first device chip, wherein each second device chip includes a second device region having a larger size than the first device region, a second peripheral region surrounding the second device region, and a second plurality of I/O pads formed in the second device region, wherein the first wafer and the second wafer are stacked; and wherein the first wafer and the second wafer are coupled to each other.
Claim 2
Dependent Claim
133 words
A wafer level stack structure, comprising: a first wafer including at least one first device chip, wherein each first device chip includes a first device region, a first peripheral region surrounding the first device region, and a first plurality of input/output (I/O) pads formed in the first device region; a second wafer including at least one second device chip approximately equal in size to the first device chip, wherein each second device chip includes a second device region having a larger size than the first device region, a second peripheral region surrounding the second device region, and a second plurality of I/O pads formed in the second device region, wherein the first wafer and the second wafer are stacked; and wherein the first wafer and the second wafer are coupled to each other.
Claim 3
Dependent Claim
45 words
The wafer level stack structure of claim 1 , wherein the size of the first device region of the at least one first device chip is larger in size than device regions of each device chip of each wafer in the wafer level stack structure.
Claim 4
Dependent Claim
22 words
The wafer level stack structure of claim 1 wherein each second peripheral region is larger than its corresponding second device chip region.
Claim 5
Dependent Claim
31 words
The wafer level stack structure of claim 1 , wherein: each of the first and second device chips include a plurality of vias; and wherein the plurality of vias are aligned.
Claim 6
Dependent Claim
27 words
The wafer level stack structure of claim 4 , wherein the plurality of vias are formed near edges of each of the first and second device chips.
Claim 7
Dependent Claim
50 words
The wafer level stack structure of claim 4 , wherein the plurality of vias of each first device chip are formed only at the first plurality of I/O pads, and wherein the plurality of vias of each second device chip are formed only at the second plurality of I/O pads.
Claim 8
Dependent Claim
24 words
The wafer level stack structure of claim 4 , wherein each of the first and second device chips contain a plurality of connection bumps.
Claim 9
Dependent Claim
26 words
The wafer level stack structure of claim 7 , wherein each of the plurality of connection bumps is formed under one of the plurality of vias.
Claim 10
Dependent Claim
12 words
A system-in-package including the wafer level stack structure of claim 1 .
Claim 11
Independent Claim
120 words
A system-in-package, comprising: a wafer level stack structure including at least one first device chip including a first device region, a first peripheral region surrounding the first device region, and a first plurality of input/output (I/O) pads formed in the first device region; and at least one second device chip including a second device region having a larger size than the first device region, a second peripheral region surrounding the second device region, and a second plurality of I/O pads formed in the second device region, wherein the at least one first device chip and the at least one second device chip have approximately equal sizes; and a common circuit board to which the wafer level stack structure is connected.
Claim 12
Independent Claim
120 words
A system-in-package, comprising: a wafer level stack structure including at least one first device chip including a first device region, a first peripheral region surrounding the first device region, and a first plurality of input/output (I/O) pads formed in the first device region; and at least one second device chip including a second device region having a larger size than the first device region, a second peripheral region surrounding the second device region, and a second plurality of I/O pads formed in the second device region, wherein the at least one first device chip and the at least one second device chip have approximately equal sizes; and a common circuit board to which the wafer level stack structure is connected.
Claim 13
Dependent Claim
17 words
The system-in-package of claim 10 , wherein each of the first and second device chips are stacked.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2010-05-07 | 2010-11-06 | 2011-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-05-07 | 2014-11-06 | 2015-05-08 | $3760.00 | Window Closed / Lapsed |
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