US7030024B2
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Dual-gate structure and method of fabricating integrated circuits having dual-gate structures
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 2002-08-23
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Granted: 2006-04-18
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Expires: 2022-08-23
Abstract
Abstract A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
Inventors
- 👤 Tuo-Hung Ho
- 👤 Ming-Fang Wang
- 👤 Chi-Chun Chen
- 👤 Chih-Wei Yang
- 👤 Liang-Gi Yao
- 👤 Chih-Chang Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:05
CPC Classifications
H; H10; H10P; H10P10/00; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
130 words
A method of fabricating a dual-gate structure on a substrate, comprising the following steps: forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; and forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively, wherein said first and second high-K dielectric layers comprise a first high-K dielectric material.
Claim 2
Independent Claim
130 words
A method of fabricating a dual-gate structure on a substrate, comprising the following steps: forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; and forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively, wherein said first and second high-K dielectric layers comprise a first high-K dielectric material.
Claim 3
Dependent Claim
74 words
The method of claim 1 , wherein said first high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said second gate structure, and wherein said second high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said first gate structure minus said target thickness for said gate dielectric for said second gate structure.
Claim 4
Dependent Claim
35 words
The method of claim 1 , wherein said first and second high-K dielectric layers are selected from the group consisting of an oxide, aluminate and silicate of tantalum, titanium, aluminum, zirconium, hafnium, yttrium and lanthanum.
Claim 5
Dependent Claim
30 words
The method of claim 1 , wherein said etching step includes a wet etch processing using HF, H 2 SO 4 , H 3 PO 4 or HNO 3 .
Claim 6
Dependent Claim
28 words
The method of claim 1 , further comprising the step of processing said first high-K dielectric layer to lower said etch rate of said first high-K dielectric layer.
Claim 7
Dependent Claim
39 words
The method of claim 5 , wherein said processing step includes the step of annealing said first high-K dielectric layer before forming said second high-K dielectric layer, whereby said etch rate of said first high-K dielectric layer is lowered.
Claim 8
Dependent Claim
21 words
The method of claim 6 , wherein said annealing step occurs in-situ with said first and second dielectric layer forming steps.
Claim 9
Dependent Claim
22 words
The method of claim 6 , wherein an anneal temperature of said anneal step is at between about 500 and 1000° C.
Claim 10
Dependent Claim
21 words
The method of claim 8 , wherein said annealing occurs in a nitrogen, ammonia, oxygen, nitric oxide or nitrous oxide ambience.
Claim 11
Independent Claim
121 words
A method of manufacturing an integrated circuit device, comprising the following steps: forming a first high-K dielectric layer in a first area defined for a first gate structure of a first device and in a second area defined for a second gate structure of a second device; processing said first high-K dielectric layer to lower an etch rate to an etchant of said first high-K dielectric layer; forming a second high-K dielectric layer in said first and second areas over said first high-K dielectric layer, said first high-K dielectric layer having a lower etch rate to said etchant relative to said second high-K dielectric layer; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer.
Claim 12
Independent Claim
121 words
A method of manufacturing an integrated circuit device, comprising the following steps: forming a first high-K dielectric layer in a first area defined for a first gate structure of a first device and in a second area defined for a second gate structure of a second device; processing said first high-K dielectric layer to lower an etch rate to an etchant of said first high-K dielectric layer; forming a second high-K dielectric layer in said first and second areas over said first high-K dielectric layer, said first high-K dielectric layer having a lower etch rate to said etchant relative to said second high-K dielectric layer; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer.
Claim 13
Dependent Claim
29 words
The method of claim 10 , further comprising the step of forming an interfacial layer between said substrate and said first high-K layer in said first and second areas.
Claim 14
Dependent Claim
19 words
The method of claim 10 , wherein said first and second high-K dielectric layers are formed from different materials.
Claim 15
Dependent Claim
39 words
The method of claim 10 , wherein said processing step includes the step of annealing said first high-K dielectric layer before forming said second high-K dielectric layer, whereby said etch rate of said first high-K dielectric layer is lowered.
Claim 16
Dependent Claim
20 words
The method of claim 13 , wherein said first and second high-K dielectric layer comprise a first high-K dielectric material.
Claim 17
Dependent Claim
43 words
The method of claim 13 , wherein an anneal temperature of said anneal step is at between about 500 and 1000° C., and said annealing occurs in situ with said forming steps in a nitrogen, ammonia, oxygen, nitric oxide or nitrous oxide ambience.
Claim 18
Dependent Claim
35 words
The method of claim 10 , wherein said first and second high-K dielectric layers are selected from the group consisting of an oxide, aluminate and silicate of tantalum, titanium, aluminum, zirconium, hafnium, yttrium and lanthanum.
Claim 19
Dependent Claim
30 words
The method of claim 16 , wherein said etching step includes a wet etch processing using HF, H 2 SO 4 , H 3 PO 4 or HNO 3 .
Claim 20
Independent Claim
143 words
A method of fabricating a dual-gate structure on a substrate, comprising the following steps: forming a first dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second dielectric layer in said first and second areas, said first dielectric layer having a lower etch rate to an etchant relative to said second dielectric layer; etching said second dielectric layer from said second area to said first dielectric layer wit said etchant; and forming a gate conductive layer in said first and second areas over said second dielectric layer and first dielectric layer, respectively, wherein said first dielectric layer is a high-K dielectric layer and said second dielectric layer is a non high-K dielectric layer, and wherein said first and second areas comprise channel areas having the same conductivity.
Claim 21
Independent Claim
143 words
A method of fabricating a dual-gate structure on a substrate, comprising the following steps: forming a first dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second dielectric layer in said first and second areas, said first dielectric layer having a lower etch rate to an etchant relative to said second dielectric layer; etching said second dielectric layer from said second area to said first dielectric layer wit said etchant; and forming a gate conductive layer in said first and second areas over said second dielectric layer and first dielectric layer, respectively, wherein said first dielectric layer is a high-K dielectric layer and said second dielectric layer is a non high-K dielectric layer, and wherein said first and second areas comprise channel areas having the same conductivity.
Claim 22
Independent Claim
135 words
A method of fabricating a dual-gate structure on a substrate, comprising the following steps: forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer; forming an interfacial layer between said substrate and said first high-K dielectric layer in said first and second areas; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; and forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively.
Claim 23
Independent Claim
135 words
A method of fabricating a dual-gate structure on a substrate, comprising the following steps: forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer; forming an interfacial layer between said substrate and said first high-K dielectric layer in said first and second areas; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; and forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively.
Claim 24
Dependent Claim
74 words
The method of claim 19 , wherein said first high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said second gate structure, and wherein said second high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said first gate structure minus said target thickness for said gate dielectric for said second gate structure.
Claim 25
Dependent Claim
19 words
The method of claim 19 , wherein said first and second high-K dielectric layers are formed from different materials.
Claim 26
Dependent Claim
31 words
The method of claim 19 , further comprising the step of annealing a remaining portion of said second high-K dielectric layer and said first high-K dielectric layer alter said etching step.
Claim 27
Dependent Claim
35 words
The method of claim 19 , wherein said first and second high-K dielectric layers are selected from the group consisting of an oxide, aluminate and silicate of tantalum, titanium, aluminum, zirconium, hafnium, yttrium and lanthanum.
Claim 28
Dependent Claim
30 words
The method of claim 19 , wherein said etching step includes a wet etch processing using HF, H 2 SO 4 , H 3 PO 4 or HNO 3 .
Claim 29
Dependent Claim
36 words
The method of claim 19 , further comprising the step of annealing said first high-K dielectric layer before forming said second high-K dielectric layer, whereby said etch rate of said first high-K dielectric layer is lowered.
Claim 30
Dependent Claim
20 words
The method of claim 25 , wherein said first and second high-K dielectric layers comprise a first high-K dielectric material.
Claim 31
Dependent Claim
21 words
The method of claim 25 , wherein said annealing step occurs in-situ with said first and second high-K dielectric forming steps.
Claim 32
Dependent Claim
22 words
The method of claim 25 , wherein an anneal temperature of said anneal step is at between about 500 and 1000° C.
Claim 33
Dependent Claim
21 words
The method of claim 28 , wherein said annealing occurs in a nitrogen, ammonia, oxygen, nitric oxide or nitrous oxide ambience.
Claim 34
Independent Claim
136 words
A method of fabricating a dual-gate structure on a substrate, comprising the following steps: forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; annealing a remaining portion of said second high-K dielectric layer and said first high-K dielectric layer after said etching step; and forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively.
Claim 35
Independent Claim
136 words
A method of fabricating a dual-gate structure on a substrate, comprising the following steps: forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure; forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer; etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant; annealing a remaining portion of said second high-K dielectric layer and said first high-K dielectric layer after said etching step; and forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively.
Claim 36
Dependent Claim
74 words
The method of claim 30 , wherein said first high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said second gate structure, and wherein said second high-K dielectric layer is deposited to have a thickness approximately equal to a target thickness for a gate dielectric for said first gate structure minus said target thickness for said gate dielectric for said second gate structure.
Claim 37
Dependent Claim
30 words
The method of claim 30 , wherein said etching step includes a wet etch processing using HF, H 2 SO 4 , H 3 PO 4 or HNO 3 .
Claim 38
Dependent Claim
35 words
The method of claim 30 , wherein said first and second high-K dielectric layers are selected from the group consisting of an oxide, aluminate and silicate of tantalum, titanium, aluminum, zirconium, hafnium, yttrium and lanthanum.
Claim 39
Dependent Claim
36 words
The method of claim 30 , further comprising the step of annealing said first high-K dielectric layer before fanning said second high-K dielectric layer, whereby said etch rate of said first high-K dielectric layer is lowered.
Claim 40
Dependent Claim
20 words
The method of claim 34 , wherein said first and second high-K dielectric layers comprise a first high-K dielectric material.
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