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US7019573B2
Expired / Lapsed
US
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DLL circuit and camcorder using DLL circuit
Assignee: Canon Inc
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Filing: 2004-05-18
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Granted: 2006-03-28
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Expires: 2024-05-18
Abstract
Abstract A DLL circuit which can prevent transition to a pseudo lock state is provided. The DLL circuit includes a delay stage to which a reference clock is input and in which variable delay elements D able to change an amount of delay are connected in a plurality of stages, a phase comparator (PH Comp) which compares the phase of the reference clock to the phase of one delay signal extracted from the delay stage, a delay control circuit which performs delay control of the delay element in the delay stage on the basis of the comparison result by the phase-comparison means, and a DFF which detects a phase relationship of at least two delay signals extracted from the delay stage to discriminate a state which is not a normal lock state and controls the delay control circuit to perform state transition to the normal lock state.
Inventors
- 👤 Yasushi Matsuno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:30
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H04; H04N; H04N23/00; H04N23/60; H04N23/67; H04N23/673; H04N25/00; H03L2207/00; H03L2207/14; H04N23/65; H04N23/651
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
145 words
A DLL circuit comprising: a delay stage to which a reference clock is input and in which delay elements able to change an amount of delay are connected in a plurality of stages; phase-comparison means for comparing a phase of the reference clock to the phase of one of delay signals extracted from said delay stage; controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase-comparison means; state transition means for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state and for controlling said controlling means to transit the state to the normal lock state; and means for controlling said controlling means so as to minimize the amount of delay in starting up the DLL circuit.
Claim 2
Dependent Claim
145 words
A DLL circuit comprising: a delay stage to which a reference clock is input and in which delay elements able to change an amount of delay are connected in a plurality of stages; phase-comparison means for comparing a phase of the reference clock to the phase of one of delay signals extracted from said delay stage; controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase-comparison means; state transition means for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state and for controlling said controlling means to transit the state to the normal lock state; and means for controlling said controlling means so as to minimize the amount of delay in starting up the DLL circuit.
Claim 3
Dependent Claim
43 words
A DLL circuit according to claim 1 , wherein reversal of a delay relationship of the phase of one of the delay signals to the phase of another delay signal is detected in detection of a phase relationship of said state transition means.
Claim 4
Dependent Claim
75 words
A DLL circuit according to claim 1 , wherein said state transition means is an edge trigger type of data input flip-flop circuit, a delay signal of a previous stage having a smaller amount of delay extracted from said delay stage is connected to a clock input of said flip-flop circuit, and the delay signal of a subsequent stage having a larger amount of delay is connected to a data input of said flip-flop circuit.
Claim 5
Dependent Claim
11 words
A camcorder having a DLL circuit according to claim 1 .
Claim 6
Dependent Claim
155 words
A DLL circuit comprising: a delay stage to which a reference clock is input and in which delay elements able to change an amount of delay are connected in a plurality of stages; phase-comparison means for comparing a phase of the reference clock to the phase of one of delay signals extracted from said delay stage; controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase-comparison means; and state transition means for controlling said controlling means so that the amount of delay of said delay stage is minimized in starting up the DLL circuit, for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state except the start-up of the DLL circuit and for controlling said controlling means to transit the state to the normal lock state.
Claim 7
Dependent Claim
155 words
A DLL circuit comprising: a delay stage to which a reference clock is input and in which delay elements able to change an amount of delay are connected in a plurality of stages; phase-comparison means for comparing a phase of the reference clock to the phase of one of delay signals extracted from said delay stage; controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase-comparison means; and state transition means for controlling said controlling means so that the amount of delay of said delay stage is minimized in starting up the DLL circuit, for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state except the start-up of the DLL circuit and for controlling said controlling means to transit the state to the normal lock state.
Claim 8
Dependent Claim
128 words
A DLL circuit comprising: a delay stage to which a reference clock is input and in which delay elements able to change an amount of delay are connected in a plurality of stages; phase-comparison means for comparing a phase of the reference clock to the phase of one of delay signals extracted from said delay stage; controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase-comparison means; and a plurality of state transition means for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state and for controlling said controlling means to transit the state to the normal lock state.
Claim 9
Dependent Claim
128 words
A DLL circuit comprising: a delay stage to which a reference clock is input and in which delay elements able to change an amount of delay are connected in a plurality of stages; phase-comparison means for comparing a phase of the reference clock to the phase of one of delay signals extracted from said delay stage; controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase-comparison means; and a plurality of state transition means for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state and for controlling said controlling means to transit the state to the normal lock state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-03-27 | 2009-09-26 | 2010-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-03-27 | 2013-09-26 | 2014-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-03-27 | 2017-09-26 | 2018-03-28 | $7700.00 | Window Closed / Lapsed |