Apparatus and method for ensuring the correct start-up and locking of a delay locked loop

Claim 2

A delay locked loop (DLL) comprising: a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal, said specified amount controlled by a control voltage applied to said delay unit; and a switch configured to clamp said control voltage to a predetermined value when said DLL is reset.

Claim 3

The DLL in claim 1 wherein said predetermined value is selected such that said delay unit will delay said input clock by less than or equal to one period.

Claim 4

The DLL in claim 1 wherein said control voltage is held by a capacitor after said DLL is reset.

Claim 5

The DLL in claim 3 wherein said control voltage is modified by a charge pump.

Claim 6

The DLL in claim 4 wherein said charge pump increases said control voltage to decrease said delay and decreases said control voltage to increase said delay.

Claim 7

The DLL in claim 5 further comprising a phase detector for controlling said charge pump responsive to a detected phase difference between said input clock signal and said delayed clock signal.

Claim 8

The DLL in claim 6 wherein, responsive to control by said phase detector, said charge pump starts increasing said control voltage responsive to a first input clock edge received at said phase detector, and stops increasing said control voltage responsive to a first delayed clock edge received at said phase detector.

Claim 9

The DLL in claim 6 wherein, responsive to control by said phase detector, said charge pump starts decreasing said control voltage responsive to a first delayed clock edge received at said phase detector, and stops decreasing said control voltage responsive to a first input clock edge received at said phase detector.

Claim 10

The DLL in claim 6 further comprising reset timing logic for ensuring that said phase detector receives a first delayed clock edge before a first input clock edge following reset of said DLL.

Claim 11

The DLL as claimed in claim 9 wherein said reset timing logic comprises: a first flip-flop having an input coupled to a predetermined binary logic state and an output coupled to an input of a second flip-flop, said first flip-flop triggered by said output clock signal; and said second flip-flop triggered by said input clock signal, and having an output configured to reset said DLL and to close said switch, thereby clamping said control voltage, when said output is in said predetermined binary logic state.

Claim 12

The DLL as claimed in claim 10 wherein said first and second flip-flops each include a reset input for receiving a non-synchronized reset signal which, when triggered, forces said outputs of each of said flip-flops to a binary logic state opposite of said predetermined binary logic state.

Claim 13

The DLL in claim 6 further comprising reset timing logic for ensuring that said phase detector receives a first input clock edge before a first delayed clock edge following reset of said DLL.

Claim 14

The DLL as claimed in claim 12 wherein said reset timing logic comprises: a first flip-flop having an input coupled to a predetermined binary logic state and an output coupled to an input of a second flip-flop, said first flip-flop triggered by said input clock signal; and said second flip-flop triggered by said output clock signal, and having an output configured to reset said DLL and to close said switch, thereby clamping said control voltage, when said output is in said predetermined binary logic state.

Claim 15

The DLL as claimed in claim 13 wherein said first and second flip-flops each include a reset input for receiving a non-synchronized reset signal which, when triggered, forces said outputs of each of said flip-flops to a binary logic state opposite of said predetermined binary logic state.

Claim 16

A delay locked loop (“DLL”) comprising: a delay unit comprising a clock input, a clock output and a control voltage input, said delay circuit configured to delay an input clock signal applied to said clock input and generate a delayed clock signal at said clock output, said delay corresponding to a control voltage applied to said control voltage input; and a switch positioned between said control voltage input and a clamping voltage source, said switch configured to electrically couple said clamping voltage source to said control voltage input when said DLL is reset.

Claim 17

A delay locked loop (“DLL”) comprising: a delay unit comprising a clock input, a clock output and a control voltage input, said delay circuit configured to delay an input clock signal applied to said clock input and generate a delayed clock signal at said clock output, said delay corresponding to a control voltage applied to said control voltage input; and a switch positioned between said control voltage input and a clamping voltage source, said switch configured to electrically couple said clamping voltage source to said control voltage input when said DLL is reset.

Claim 18

The DLL of claim 15 further comprising a capacitor electrically coupled to said control voltage input, and configured to temporarily store said clamping voltage applied to said control voltage input after said switch de-couples said clamping voltage source from said control voltage input.

Claim 19

The DLL of claim 16 further comprising a phase detector having an input clock signal input and a delayed clock signal input, configured to detect phase differences between said delayed clock signal and said input clock signal; and a charge pump for modifying said voltage stored in said capacitor responsive to a control signal from said phase detector.

Claim 20

The DLL of claim 17 wherein said charge pump is configured to modify said voltage stored in said capacitor responsive to a phase difference between said input clock signal and said delayed clock signal detected by said phase detector.

Claim 21

The DLL of claim 18 wherein, responsive to control by said phase detector, said charge pump starts increasing said control voltage responsive to a first input clock edge received at said phase detector, and stops increasing said control voltage responsive to a first delayed clock edge received at said phase detector.

Claim 22

The DLL in claim 17 further comprising reset timing logic for ensuring that said phase detector receives a first delayed clock edge before a first input clock edge following reset of said DLL.

Claim 23

The DLL as claimed in claim 20 wherein said reset timing logic comprises: a first flip-flop having an input coupled to a predetermined binary logic state and an output coupled to an input of a second flip-flop, said first flip-flop triggered by said output clock signal; and said second flip-flop triggered by said input clock signal, and having an output configured to reset said DLL and to close said switch, thereby clamping said control voltage, when said output is in said predetermined binary logic state.

Claim 24

The DLL as claimed in claim 21 wherein said first and second flip-flops each include a reset input for receiving a non-synchronized reset signal which, when triggered, forces said outputs of each of said flip-flops to a binary logic state opposite of said predetermined binary logic state.

Claim 25

A machine-readable medium having code stored thereon which defines an integrated circuit (IC), said IC comprising: a delay unit comprising a clock input, a clock output and a control voltage input, said delay circuit configured to delay an input clock signal applied to said clock input and generate a delayed clock signal at said clock output, said delay corresponding to a control voltage applied to said control voltage input; and a switch positioned between said control voltage input and a clamping voltage source, said switch configured to electrically couple said clamping voltage source to said control voltage input when said IC is reset.

Claim 26

A machine-readable medium having code stored thereon which defines an integrated circuit (IC), said IC comprising: a delay unit comprising a clock input, a clock output and a control voltage input, said delay circuit configured to delay an input clock signal applied to said clock input and generate a delayed clock signal at said clock output, said delay corresponding to a control voltage applied to said control voltage input; and a switch positioned between said control voltage input and a clamping voltage source, said switch configured to electrically couple said clamping voltage source to said control voltage input when said IC is reset.

Claim 27

The machine readable medium of claim 23 further comprising code which defines a capacitor electrically coupled to said control voltage input, and configured to temporarily store said clamping voltage applied to said control voltage input after said switch de-couples said clamping voltage source from said control voltage input.

Claim 28

The machine readable medium of claim 24 further comprising code which defines a phase detector having an input clock signal input and a delayed clock signal input, configured to detect phase differences between said delayed clock signal and said input clock signal; and a charge pump for modifying said voltage stored in said capacitor responsive to a control signal from said phase detector.

Claim 29

The machine readable medium of claim 25 wherein said charge pump is configured to modify said voltage stored in said capacitor responsive to a phase difference between said input clock signal and said delayed clock signal detected by said phase detector.

Claim 30

The machine readable medium of claim 25 wherein, responsive to control by said phase detector, said charge pump starts increasing said control voltage responsive to a first input clock edge received at said phase detector, and stops increasing said control voltage responsive to a first delayed clock edge received at said phase detector.

Claim 31

The machine readable medium of claim 27 further comprising code which defines reset timing logic for ensuring that said phase detector receives a first delayed clock edge before a first input clock edge following reset of said DLL.

Claim 32

The machine readable medium of claim 24 where in said reset timing logic comprises: a first flip-flop having an input coupled to a predetermined binary logic state and an output coupled to an input of a second flip-flop, said first flip-flop triggered by said output clock signal; and said second flip-flop triggered by said input clock signal, and having an output configured to reset said DLL and to close said switch, thereby clamping said control voltage, when said output is in said predetermined binary logic state.

Claim 33

The machine readable medium of claim 24 further comprising code which defines where in s aid first and second flip-flops each include a reset input for receiving a non-synchronized reset signal which, when triggered, forces said outputs of each of said flip-flops to a binary logic state opposite of said predetermined binary logic state.

Claim 34

The machine readable medium of claim 23 wherein said code defining an IC is VHDL code.

Claim 35

The machine readable medium of claim 23 wherein said code defining an IC is Register Transfer Level (“RTL”) netlist code.

Claim 36

The machine readable medium of claim 23 wherein said code defining an IC is GDSII code.