US5202978A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-test circuit of information processor
Assignee: Toshiba Corp
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Filing: 1989-03-15
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Granted: 1993-04-13
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Expires: 2009-03-15
Abstract
Abstract A self-test circuit for an information processor employing a microprogram control system carries out a self-test inside the information processor. The self-test circuit comprises a test data generator for generating test data which are written into specific fields of primary test microinstructions. The self-test circuit further includes a selection controller. The selection controller receives microinstructions, including the primary test microinstructions as well as the test data generated by the test data generator. During the self-test, the selection controller masks specific fields of each primary test microinstruction and supplies the test data from the test data generator in the masked specific fields to form secondary test microinstructions, which are sent to a microinstruction register. With this arrangement, the test data from the test data generator are put in the specific fields of each primary test microinstruction to generate a secondary test microinstruction so that the number and kinds of primary test microinstructions, required for testing functional blocks in the information processor will be reduced.
Inventors
- 👤 Yasuyuki Nozuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:34
CPC Classifications
G; G06; G06F; G06F9/00; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F9/06; G06F9/22; G06F9/226
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
154 words
A self-test circuit of an information processor including a microprogram control system, the self-test circuit carrying out a self-test inside the information processor and comprising: test data generating means for generating test data to be written in specific fields of each of primary test microinstructions; and selection controlling means for receiving microinstructions including the primary test microinstructions as well as receiving the test data from said test data generating means, said selection control means masking the specific fields of each primary test microinstruction and supplying the test data from said test data generating means to the masked specific fields during the self-test to form a secondary test microinstruction, the number of the primary test microinstructions being minimized because the test data from said test data generating means are used as the data of the specific fields of the primary test microinstructions, wherein said information processor and said self-test circuit form an integral operating unit.
Claim 2
Dependent Claim
154 words
A self-test circuit of an information processor including a microprogram control system, the self-test circuit carrying out a self-test inside the information processor and comprising: test data generating means for generating test data to be written in specific fields of each of primary test microinstructions; and selection controlling means for receiving microinstructions including the primary test microinstructions as well as receiving the test data from said test data generating means, said selection control means masking the specific fields of each primary test microinstruction and supplying the test data from said test data generating means to the masked specific fields during the self-test to form a secondary test microinstruction, the number of the primary test microinstructions being minimized because the test data from said test data generating means are used as the data of the specific fields of the primary test microinstructions, wherein said information processor and said self-test circuit form an integral operating unit.
Claim 3
Dependent Claim
50 words
The self-test circuit as claimed in claim 1, wherein said selection controlling means are not applied to specific fields of the microinstructions designating microsequence functions, or are so constituted to pass such said specific field during the self-test in the same manner as the normal operation of the information processor.
Claim 4
Dependent Claim
21 words
The self-test circuit as claimed in claim 1, wherein said test data generating means comprises a counter for outputting count data.
Claim 5
Dependent Claim
22 words
The self-test circuit as claimed in claim 1, wherein said test data generating means comprises a shift register for outputting shifted data.
Claim 6
Dependent Claim
81 words
The self-test circuit as claimed in claim 1, wherein the said selection controlling means comprises: controlling means for supplying select signals, the select signals specifying the specific fields of each primary test microinstruction as well as specifying test data to be written in the specific fields; and a plurality of selectors for masking the specific fields of the primary test microinstruction and supplying the test data to the masked specific fields according to the select signals sent from the controlling means.
Claim 7
Dependent Claim
28 words
The self-test circuit as claimed in claim 1, wherein the microinstructions including the primary test microinstructions are supplied from a microinstruction storage ROM to said selection control means.
Claim 8
Dependent Claim
58 words
The self-test circuit as claimed in claim 1, further comprising a microinstruction storage memory storing said microinstructions, including the primary test microinstructions, and a microinstruction register temporarily storing said microinstructions including the secondary test microinstructions, and supplying them to the information processor, wherein said selection control means is positioned between said microinstruction storage means and said microinstruction processor.
Claim 9
Dependent Claim
24 words
The self-test circuit as claimed in claim 1, wherein said test data generating means comprises a circuit for outputting count data and shifted data.
Claim 10
Dependent Claim
18 words
The self-test circuit as claimed in claim 1, wherein said test data generating means comprises a linear-feedback shift-register.
References Cited (Backward Citations)
US3568155A
Cited
US4048481A
Cited
GB2017361A
Cited
US4180861A
Cited
US4313200A
Cited
US4414665A
Cited
US4520439A
Cited
US4441182A
Cited
US4797808A
Cited
US4490783A
Cited
US4502127A
Cited
US4503536A
Cited
US4597080A
Cited
US4641308A
Cited
US4745574A
Cited
EP0184158A2
Cited
US4736375A
Cited
US4920538A
Cited
US4768195A
Cited
FR2589264A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |