US4797808A
Expired / Lapsed
US
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Microcomputer with self-test of macrocode
Assignee: Texas Instruments Inc
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Filing: 1981-06-22
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Granted: 1989-01-10
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Expires: 2001-06-22
Abstract
Abstract A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A macrocode word is fetched from an on-chip ROM and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the microcode store based on this macrocode word. A check-code based on some function of all macrocode bits is stored in on-chip ROM upon manufacture. To test a device after fabrication is complete, a test program (resident in ROM or downloaded into on-chip RAM) is executed to address all bytes of macrocode and perform some cummulative function on it via the ALU to see if the same check-code is produced. If so, an output indicates a good unit.
Inventors
- 👤 Jeffrey D. Bellay
- 👤 Kevin C. McDonough
- 👤 Michael W. Patrick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:55
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814; G06F11/07; G06F11/08; G06F11/10; G06F11/1004; G06F11/2273
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
244 words
A microcomputer device formed in a single semiconductor integrated circuit (10) with internal self-test of instruction code, comprising: a CPU having an ALU (14) with a plurality of address/data registers (15) and bus means (16) for accessing the registers and input/output for the ALU, control means including an instruction register (IR) for defining the operation of the CPU in response to multi-bit instruction code words, said control means including means (17) for generating control signals from said instruction code words which are transferred into said instruction register (IR), program storage means (11) in the integrated circuit for permanently storing a plurality of instruction code words and a check-code representation of all of the bits in all of said plurality of instruction code words, read/write storage means (12) in the integrated circuit (10) for temporarily storing data or storing other instruction code words, means for transferring (MD) sequences of said instruction code words into said instruction register either from said program storage means (11) or from said read/write storage means (12), said CPU and control means accessing said other instruction code words from said read/write memory (12) to perform a sequential operation on all of the bits in all of said plurality of instruction code words and to generate a first output (30) from the device if a result of such operation corresponds to said check-code representation and a second output (30) from the device if such result does not correspond to said check-code representation.
Claim 2
Dependent Claim
244 words
A microcomputer device formed in a single semiconductor integrated circuit (10) with internal self-test of instruction code, comprising: a CPU having an ALU (14) with a plurality of address/data registers (15) and bus means (16) for accessing the registers and input/output for the ALU, control means including an instruction register (IR) for defining the operation of the CPU in response to multi-bit instruction code words, said control means including means (17) for generating control signals from said instruction code words which are transferred into said instruction register (IR), program storage means (11) in the integrated circuit for permanently storing a plurality of instruction code words and a check-code representation of all of the bits in all of said plurality of instruction code words, read/write storage means (12) in the integrated circuit (10) for temporarily storing data or storing other instruction code words, means for transferring (MD) sequences of said instruction code words into said instruction register either from said program storage means (11) or from said read/write storage means (12), said CPU and control means accessing said other instruction code words from said read/write memory (12) to perform a sequential operation on all of the bits in all of said plurality of instruction code words and to generate a first output (30) from the device if a result of such operation corresponds to said check-code representation and a second output (30) from the device if such result does not correspond to said check-code representation.
Claim 3
Dependent Claim
24 words
A device according to claim 1 wherein said program storage means includes a semiconductor read-only memory array storing said plurality of instruction code words.
Claim 4
Dependent Claim
40 words
A device according to claim 2 wherein said read/write storage means is a semiconductor read/write array and said CPU transfers addresses from said address/data registers to either the read/write memory array or the read-only memory array via said bus means.
Claim 5
Dependent Claim
63 words
A device according to claim 3 wherein operation of said CPU is defined by instruction code words of N bits in width transferred into said instruction register, and said address/data registers and said bus means are N bits in width, and wherein instruction code words are stored in said read-only memory array or read/write memory array as words of N bits in width.
Claim 6
Dependent Claim
33 words
A device according to claim 4 wherein said other instruction code words in said read/write memory array and said check-code representation are addressed from said CPU using said address/data registers and bus means.
Claim 7
Independent Claim
158 words
A method testing an integrated semiconductor device of the type containing a digital processor having a plurality of different processor functions and a plurality of multibit instruction words defining the different processor function stored in said device, comprising the steps of: storing on said device a multibit code representing a commulative function of all of the bits in all of said plurality of multibit instruction words, transferring into said device a test routine made up of instruction words, and storing said test routine temporarily in said device, activating the device using said test routine to perform arithmetic or logic operations via said digital processor on all of said plurality of multibit instruction words to produce a result, producing a first electrical signal at output terminals of said device is said result corresponds to said multibit code, and producing a second electrical signal at output terminals of said device if said result does not correspond to said multibit code.
Claim 8
Independent Claim
158 words
A method testing an integrated semiconductor device of the type containing a digital processor having a plurality of different processor functions and a plurality of multibit instruction words defining the different processor function stored in said device, comprising the steps of: storing on said device a multibit code representing a commulative function of all of the bits in all of said plurality of multibit instruction words, transferring into said device a test routine made up of instruction words, and storing said test routine temporarily in said device, activating the device using said test routine to perform arithmetic or logic operations via said digital processor on all of said plurality of multibit instruction words to produce a result, producing a first electrical signal at output terminals of said device is said result corresponds to said multibit code, and producing a second electrical signal at output terminals of said device if said result does not correspond to said multibit code.
Claim 9
Dependent Claim
60 words
A method according to claim 6 wherein said step of activating the device causes the digital processor to operate on words N bits wide accessed from a read/write memory on said device, where N is an integer, and wherein each of said plurality of multibit instruction words is N bits wide and accessed from a read-only memory on said device.
Claim 10
Dependent Claim
30 words
A method according to claim 6 wherein the step of transferring into said device is performed by executing a loading routine defined by instruction words stored external to the device.
Claim 11
Dependent Claim
32 words
A method according to claim 8 wherein said multibit code representing a cummulative function is in the format of the instruction words and is stored in a read-only memory on the device.
Claim 12
Dependent Claim
27 words
A method according to claim 9 including the step of producing a sequence of microcode controls in said device said produced for each of said instruction words.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-10 | 1992-07-11 | 1993-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-10 | 1996-07-11 | 1997-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-10 | 2000-07-11 | 2001-01-10 | $7700.00 | Window Closed / Lapsed |