Delay locked loop having a mis-lock detecting circuit

Claim 2

A delay locked loop comprising: a voltage-controlled delay section configured to receive a reference signal and a delay control signal, including, a plurality of voltage controlled delay circuits connected in series, each voltage controlled delay circuit having a delay time, and configured to delay sequentially the reference signal in accordance with the delay control signal, thereby to output a first delayed signal through an (n−1) th delayed signal to an n th delayed signal that are sequentially delayed in time; a phase comparator configured to receive the first delayed signal and the n−1 th delayed signal, detect a phase difference between the first and n−1 th delayed signals and output an error signal representing the phase difference detected; a filter circuit configured to receive the error signal from the phase comparator, extract a direct-current component from the error signal, and supply the direct-current component, as the delay control signal, to the voltage controlled delay circuit; and a mis-lock detecting circuit configured to generate a plurality of pulse signals, each pulse signal having a width corresponding to a difference in a delay time between adjacent delay signals of the first to n th delayed signals, to add the pulse signals to generate a sum signal, and to compare the sum signal with the reference signal in terms of a number of pulses contained in the sum signal and reference signal per unit time, thereby detecting a mislocked state of the voltage-controlled delay section.

Claim 3

A delay locked loop according to claim 1 , wherein the delay time of each of the first to n th delayed signals output from the voltage-controlled delay section is controlled by the delay control signal so that a delay time between the first and n−1 th delayed signals is substantially equal to a one-cycle time of the reference signal while the voltage-controlled delay section remains normally locked.

Claim 4

A delay locked loop according to claim 1 , wherein the mis-lock detecting circuit comprises: a mis-lock detect signal generating circuit configured to detect a mis-locked state of the voltage-controlled delay section and output at least one mis-lock detect signal upon detection of the mis-locked state of the voltage-controlled delay section; and a mis-lock control signal generating circuit configured to generate, from said at least one mis-lock detect signal, a mis-lock control signal configured to set an output voltage of the phase comparator.

Claim 5

A delay locked loop according to claim 3 , wherein said at least one mis-lock detect signal output from the mis-lock detect signal generating circuit is composed of a first mis-lock detect signal and a second mis-lock detect signal, said first mis-lock detect signal is output from the mis-lock detect signal generating circuit when the voltage-controlled delay section remains locked while the delay time between the first and n−1 th delayed signals is shorter than a delay time which exists between the first and n−1 th delay signals while the voltage-controlled delay section remains normally locked and said second mis-lock detect signal is output from the mis-lock detect signal generating circuit when the voltage-controlled delay section remains locked while the delay time between the first and n−1 th delayed signals is longer than a delay time which exists between the first and n−1 th delay signals while the voltage-controlled delay section remains normally locked.

Claim 6

A delay locked loop according to claim 4 , wherein the mis-lock detect signal generating circuit comprises: a frequency-dividing circuit configured to receive the signal output from the adder circuit and dividing a frequency of the signal by a predetermined ratio, thereby to output a signal; a plurality of pulse signal generating circuits configured to receive an adjacent two of the first to n th delayed signals and generate a plurality of pulse signals, each pulse signal having a width corresponding to a difference in delay time between adjacent two of the first to nth delayed signals; an adder circuit configured to add the pulse signals generated by the pulse signal generating circuits; a first counter circuit configured to receive the reference signal and count pulses of the reference signal, thereby to output a first count signal; a first comparing circuit configured to receive the first count signal output from the first counter circuit and compare the first count signal with a first fixed value, to output a first signal when the first count signal has a value equal to the first fixed value; a second counter circuit configured to receive the signal output from the frequency-dividing circuit and count pulses of the signal, thereby to output a second count signal; a second comparing circuit configured to receive the second count signal output from the second counter circuit, to compare the second count signal with a second fixed value smaller than the first fixed value, and to output a second signal when the second count signal has a value equal to the second fixed value; a third comparing circuit configured to receive the second count signal output from the second counter circuit, to compare the second count signal with a third fixed value larger than the first fixed value, and to output a third signal when the second count signal has a value equal to the third fixed value; a first logic circuit configured to receive the first and second signals output from the first and second comparing circuits and generate the first mis-lock detect signal from the first and second signals output from the first and second comparing circuits; and a second logic circuit configured to receive the first and third signals output from the first and third comparing circuits and generate the second mis-lock detect signal from the first and third signals output from the first and third comparing circuits.

Claim 7

A delay locked loop according to claim 5 , wherein each of the pulse signal generating circuits comprises: two NOR circuits each including, a first input terminal, and a second input terminal, wherein said NOR circuits are configured as a flip-flop circuit in which two adjacent signals are supplied respectively to the first input terminals of the NOR circuits and a signal output from each NOR circuit is supplied to the second input terminal of the other NOR circuit.

Claim 8

A delay locked loop according to claim 5 , wherein the first and second logic circuits are AND circuits.

Claim 9

A delay locked loop according to claim 5 , wherein the first fixed value is N, where N is 1 or a greater positive integer, the second fixed value is 0.5N, and the third fixed value is 1.5N.

Claim 10

A delay locked loop according to claim 5 , wherein the mis-lock control signal generating circuit comprises: a first flip-flop circuit having a set terminal and a reset terminal, configured to receive the signals output from the first and second logic circuits at the set terminal and reset terminal, respectively, and output a first mis-lock control signal which sets an output voltage of the phase comparator at a high potential; and a second flip-flop circuit having a set terminal and a reset terminal, configured to receive at the set terminal the signal output from the second logic circuit, and to receive at the reset terminal any one of the first to n−1 th delayed signals, and to output a second mis-lock control signal which sets the output voltage of the phase comparator at a low potential.

Claim 11

A delay locked loop according to claim 4 , wherein the mis-lock detect signal generating circuit comprises: a plurality of pulse signal generating circuits configured to receive an adjacent two of the first to n th delayed signals and generate a plurality of pulse signals, each pulse signal having a width corresponding to a difference in delay time between adjacent two of the first to n th delayed signals; an adder circuit configured to add the pulse signals generated by the pulse signal generating circuits; a frequency-dividing circuit configured to receive the signal output from the adder circuit and divide a frequency of the signal by a predetermined ratio, thereby to output a signal; a first counter circuit configured to receive the reference signal and count pulses of the reference signal, thereby to output a first count signal; a first comparing circuit configured to receive the first count signal output from the first counter circuit, and to compare the first count signal with a first fixed value, and to output a first signal when the first count signal has a value equal to the first fixed value; a first logic circuit configured to receive the signal output from the frequency-dividing circuit and output the output signal of the frequency-dividing circuit until the first comparing circuit outputs the first signal upon detection that the first count signal has a value equal to the first fixed value; a second counter circuit configured to receive the signal output from the first logic circuit, to count pulses of the signal, and to output a second count signal; a second comparing circuit configured to receive the second count signal output from the second counter circuit, to compare the second count signal with a second fixed value smaller than the first fixed value, and to output a second signal when the second count signal has a value equal to the second fixed value; a third comparing circuit configured to receive the second count signal output from the second counter circuit, to compare the second count signal with a third fixed value larger than the first fixed value, and to output a third signal when the second count signal has a value equal to the third fixed value; a first latch circuit configured to receive and latch the first signal output from the first comparing circuit; a second latch circuit configured to receive and latch the second signal output from the second comparing circuit; a third latch circuit configured to receive and latch the third signal output from the third comparing circuit; a fourth latch circuit configured to receive and latch a signal output from the first latch circuit; a second logic circuit configured to receive signals output from the first and second latch circuits and generate the first mis-lock detect signal from the signals output from the first and second latch circuits; and a third logic circuit configured to receive signals output from the first and third latch circuits and generate the second mis-lock detect signal from the signals output from the first and third latch circuits.

Claim 12

A delay locked loop according to claim 10 , wherein each of the pulse signal generating circuits comprises: two NOR circuits each including, a first input terminal, and a second input terminal, wherein said NOR circuits are configured as a flip-flop circuit in which two adjacent delayed signals are supplied respectively to the first input terminals of the NOR circuits and a signal output from each NOR circuit is supplied to the second input terminal of the other NOR circuit.

Claim 13

A delay locked loop according to claim 10 , wherein the first logic circuit is a NOR circuit.

Claim 14

A delay locked loop according to claim 10 , wherein the second and third logic circuits are AND circuits.

Claim 15

A delay locked loop according to claim 10 , wherein the first fixed value is N, where N is 1 or a greater positive integer, the second fixed value is 0.5N, and the third fixed value is 1.5N.

Claim 16

A delay locked loop according to claim 1 , wherein each of the controlled delay circuits has: a first voltage-applying node for applying a power-supply voltage; a second voltage-applying node for applying a ground voltage; a first CMOS inverting circuit comprising a first output node, first and second MOS transistors of first channel type, each having a source-drain path and a gate, and third and fourth MOS transistors of second channel type, each having a source-drain path and a gate, wherein the source-drain paths of the first and second MOS transistors are connected in series between the first voltage-applying node and the first output node, the gates of the first and second MOS transistors are supplied with a first control signal generated from the delay control signal and a signal output from the preceding controlled delay circuit respectively, the source-drain paths of the third and fourth MOS transistors are connected in series between the first output node and the second voltage-applying node, and the gates of the third and fourth MOS transistors are supplied with a second control signal generated from the delay control signal and the signal output from the preceding controlled delay circuit respectively; and a second CMOS inverting circuit comprising a second output node, fifth and sixth MOS transistors of first channel type, each having a source-drain path and a gate, and seventh and eighth MOS transistors of second channel type, each having a source-drain path and a gate, wherein the source-drain paths of the fifth and sixth MOS transistors are connected in series between the first voltage-applying node and the second output node, the gates of the fifth and sixth MOS transistors are supplied with the first control signal and a signal obtained at the first output node respectively, the source-drain paths of the seventh and eighth MOS transistors are connected in series between the second output node and the second voltage-applying node, the gates of the seventh and eighth MOS transistors are supplied with the second control signal and the signal obtained at the first output node, and a signal obtained at the second output node is supplied to the following controlled delay circuit.