Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: a delay circuit including a plurality of delay elements series-connected to each other, each having a delay time which is controlled in accordance with a voltage; a phase comparison circuit for comparing a phase of an m-th clock signal and a phase of an (m+N)th clock signal in said delay circuit to obtain a phase difference, where m is not less than 1 and N is not less than 1; a comparison control signal generating circuit for generating a comparison control signal so as to control said phase comparison circuit to generate a predetermined voltage when said phase difference between the phase of said m-th clock signal and the phase of said (m+N)th clock signal exceeds a predetermined range; and a filter circuit for filtering a voltage generated by said phase comparison circuit and applying said filtered voltage to said plurality of delay elements of said delay circuit.

Claim 3

A semiconductor integrated circuit comprising: a delay circuit including a plurality of delay elements series-connected to each other, each having a delay time which is controlled in accordance with a voltage; a phase comparison circuit for comparing a phase of a clock signal and a phase of another clock signal in said delay circuit to obtain a phase difference; a comparison control signal generating circuit for generating a comparison control signal so as to control said phase comparison circuit to generate a predetermined voltage when said phase difference between the phase of said clock signal and the phase of and said another clock signal exceeds a predetermined range; and a filter circuit for filtering a voltage generated by said phase comparison circuit and applying said filtered voltage to said plurality of delay elements of said delay circuit; wherein said comparison control signal generating circuit controls said phase comparison circuit to generate a first predetermined voltage when said phase difference is smaller than 2π and within a first predetermined range and to generate a second predetermined voltage when said phase difference is greater than 2π and within a second predetermined range.

Claim 4

A semiconductor integrated circuit comprising: a delay circuit including a plurality of delay elements series-connected to each other, each having a delay time which is controlled in accordance with a voltage; a phase comparison circuit for comparing a phase of a clock signal and a phase of another clock signal in said delay circuit to obtain a phase difference; a comparison control signal generating circuit for generating a comparison control signal so as to control said phase comparison circuit to generate a predetermined voltage when said phase difference between the phase of said clock signal and the phase of and said another clock signal exceeds a predetermined range; and a filter circuit for filtering a voltage generated by said phase comparison circuit and applying said filtered voltage to said plurality of delay elements of said delay circuit; wherein said comparison control signal generating circuit controls said phase comparison circuit to generate a first predetermined voltage when said phase difference is smaller than 2π and within a first predetermined range and to generate a second predetermined voltage when said phase difference is greater than 2π and within a second predetermined range.

Claim 5

A semiconductor integrated circuit comprising: a delay circuit including a plurality of delay elements series-connected to each other, each having a delay time which is controlled in accordance with a voltage; a phase comparison circuit for comparing a phase of a clock signal and a phase of another clock signal in said delay circuit to obtain a phase difference; a comparison control signal generating circuit for generating a comparison control signal so as to control said phase comparison circuit to generate a predetermined voltage when said phase difference between the phase of said clock signal and the phase of said another clock signal exceeds a predetermined range; and a filter circuit for filtering a voltage generated by said phase comparison circuit and applying said filtered voltage to said plurality of delay elements of said delay circuit; wherein said phase comparison circuit comprises: a first dynamic D latch circuit having a clock signal input terminal to be supplied with said clock signal which is output from a predetermined one of said plurality of delay elements; a second dynamic D latch circuit having a clock signal input terminal to be supplied with said another clock signal which is output from another predetermined one of said plurality of delay elements; a first logic circuit for supplying data to a data input terminal of said first dynamic D latch circuit on the basis of output signals of said first and second dynamic D latch circuits; a second logic circuit for supplying data to a data input terminal of said second dynamic D latch circuit on the basis of the output signals of said first and second dynamic D latch circuits; and a circuit for generating the voltage to be output from said phase comparison circuit on the basis of the output signals of said first and second dynamic D latch circuits.

Claim 6

A semiconductor integrated circuit comprising: a delay circuit including a plurality of delay elements series-connected to each other, each having a delay time which is controlled in accordance with a voltage; a phase comparison circuit for comparing a phase of a clock signal and a phase of another clock signal in said delay circuit to obtain a phase difference; a comparison control signal generating circuit for generating a comparison control signal so as to control said phase comparison circuit to generate a predetermined voltage when said phase difference between the phase of said clock signal and the phase of said another clock signal exceeds a predetermined range; and a filter circuit for filtering a voltage generated by said phase comparison circuit and applying said filtered voltage to said plurality of delay elements of said delay circuit; wherein said phase comparison circuit comprises: a first dynamic D latch circuit having a clock signal input terminal to be supplied with said clock signal which is output from a predetermined one of said plurality of delay elements; a second dynamic D latch circuit having a clock signal input terminal to be supplied with said another clock signal which is output from another predetermined one of said plurality of delay elements; a first logic circuit for supplying data to a data input terminal of said first dynamic D latch circuit on the basis of output signals of said first and second dynamic D latch circuits; a second logic circuit for supplying data to a data input terminal of said second dynamic D latch circuit on the basis of the output signals of said first and second dynamic D latch circuits; and a circuit for generating the voltage to be output from said phase comparison circuit on the basis of the output signals of said first and second dynamic D latch circuits.

Claim 7

A semiconductor integrated circuit comprising: a delay circuit including a plurality of delay elements series-connected to each other, each having a delay time which is controlled in accordance with a voltage; a phase comparison circuit for comparing a phase of a clock signal and a phase of another clock signal in said delay circuit to obtain a phase difference; a comparison control signal generating circuit for generating a comparison control signal so as to control said phase comparison circuit to generate a predetermined voltage when said phase difference between the phase of said clock signal and the phase of said another clock signal exceeds a predetermined range; a filter circuit for filtering a voltage generated by said phase comparison circuit and applying said filtered voltage to said plurality of delay elements of said delay circuit; and a serial-parallel conversion circuit for converting serial data into parallel data by using multi-phase clock signals outputted from said plurality of delay elements.

Claim 8

A semiconductor integrated circuit comprising: a delay circuit including a plurality of delay elements series-connected to each other, each having a delay time which is controlled in accordance with a voltage; a phase comparison circuit for comparing a phase of a clock signal and a phase of another clock signal in said delay circuit to obtain a phase difference; a comparison control signal generating circuit for generating a comparison control signal so as to control said phase comparison circuit to generate a predetermined voltage when said phase difference between the phase of said clock signal and the phase of said another clock signal exceeds a predetermined range; a filter circuit for filtering a voltage generated by said phase comparison circuit and applying said filtered voltage to said plurality of delay elements of said delay circuit; and a serial-parallel conversion circuit for converting serial data into parallel data by using multi-phase clock signals outputted from said plurality of delay elements.

Claim 9

A multi-phase clock generating method comprising the steps of: outputting multi-phase clock signals having different phases from each other; comparing a phase of a clock signal and a phase of another clock signal in said multi-phase clock signals to obtain a phase difference; and controlling a voltage to decrease a signal delay time until said phase difference between the phase of said clock signal and the phase of said another clock signal becomes equal to 2π in a case where said phase difference is greater than 2π and in a predetermined range, and controlling said voltage to increase said signal delay time until said phase difference becomes equal to 2π in a case where said phase difference is smaller than 2π and in a predetermined range; wherein said clock signal and said another clock signal are directly compared to lock a delay-locked loop such that phase differences between phases of two adjacent clock signals included in said multi-phase clock signals become 1/N times a period of a transmission clock signal.

Claim 10

A multi-phase clock generating method comprising the steps of: outputting multi-phase clock signals having different phases from each other; comparing a phase of a clock signal and a phase of another clock signal in said multi-phase clock signals to obtain a phase difference; and controlling a voltage to decrease a signal delay time until said phase difference between the phase of said clock signal and the phase of said another clock signal becomes equal to 2π in a case where said phase difference is greater than 2π and in a predetermined range, and controlling said voltage to increase said signal delay time until said phase difference becomes equal to 2π in a case where said phase difference is smaller than 2π and in a predetermined range; wherein said clock signal and said another clock signal are directly compared to lock a delay-locked loop such that phase differences between phases of two adjacent clock signals included in said multi-phase clock signals become 1/N times a period of a transmission clock signal.

Claim 11

A data receiving method comprising the steps of: outputting multi-phase clock signals having different phases from each other; comparing a phase of a clock signal and a phase of another clock signal in said multi-phase clock signals to obtain a phase difference; controlling a voltage to decrease a signal delay time until said phase difference between the phase of said clock signal and the phase of said another clock signal becomes equal to 2π in a case where said phase difference is greater than 2π and in a predetermined range, and controlling said voltage to increase said signal delay time until said phase difference becomes equal to 2π in a case where said phase difference is smaller than 2π and in a predetermined range; and converting serial data into parallel data by using said multi-phase clock signals phases of which are controlled.

Claim 12

A data receiving method comprising the steps of: outputting multi-phase clock signals having different phases from each other; comparing a phase of a clock signal and a phase of another clock signal in said multi-phase clock signals to obtain a phase difference; controlling a voltage to decrease a signal delay time until said phase difference between the phase of said clock signal and the phase of said another clock signal becomes equal to 2π in a case where said phase difference is greater than 2π and in a predetermined range, and controlling said voltage to increase said signal delay time until said phase difference becomes equal to 2π in a case where said phase difference is smaller than 2π and in a predetermined range; and converting serial data into parallel data by using said multi-phase clock signals phases of which are controlled.