Analog delay locked loop with tracking analog-digital converter

Claim 1

An analog DLL which buffers an external clock signal and uses the buffered clock signal as a reference clock signal, comprising: a delay model for delaying a delayed clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges in response to an outputted signal from the phase comparator; a loop filter for generating a reference voltage which is determined by a quantity of charges inputted from the charge pump; a voltage control delay line which delays the reference clock signal for a predetermined time, and outputs the delayed clock signal to the delay model, where the predetermined time is determined by the reference voltage; and a tracking analog-digital converter which converts the reference voltage to a digital value, and stores the digital value for keeping the reference voltage safely, and outputs a tracking voltage which corresponds to the digital value to the loop filter, wherein the tracking analog-digital converter includes: a voltage comparator for comparing the reference voltage with the tracking voltage; a counting means for counting in response to an outputted signal from the voltage comparator, and for outputting an counting signal; a register for storing a digital value which corresponds to the counting signal; and a digital-analog converting means for generating a voltage which corresponds to the digital value, and for outputting the voltage as the tracking voltage.