US6275079B1 — Analog delay locked loop circuit

Claim 1

Independent Claim 140 words

An analog delay locked loop circuit comprising: a phase detector for detecting a phase difference between a first clock signal and a fed-back second clock signal; a charge pump for carrying out a pumping operation according to an output from the phase detector; a low pass filter for filtering an output from the charge pump, and for outputting a control voltage; a supply power selecting unit for outputting a first supply power or a second supply power in accordance with a supply power selecting signal; a voltage control delay unit for receiving a supply power selected in the supply power selecting unit, and for delaying the first clock signal in accordance with the control voltage from the low pass filter; and a driver for amplifying an output from the voltage control delay unit, and for generating the second clock signal.

Claim 2

Dependent Claim 140 words

An analog delay locked loop circuit comprising: a phase detector for detecting a phase difference between a first clock signal and a fed-back second clock signal; a charge pump for carrying out a pumping operation according to an output from the phase detector; a low pass filter for filtering an output from the charge pump, and for outputting a control voltage; a supply power selecting unit for outputting a first supply power or a second supply power in accordance with a supply power selecting signal; a voltage control delay unit for receiving a supply power selected in the supply power selecting unit, and for delaying the first clock signal in accordance with the control voltage from the low pass filter; and a driver for amplifying an output from the voltage control delay unit, and for generating the second clock signal.

Claim 3

Dependent Claim 27 words

The circuit according to claim 1 , wherein the first clock signal is an external clock signal, and the second clock signal is an internal clock signal.

Claim 4

Dependent Claim 27 words

The circuit according to claim 1 , wherein the first supply power is at a Vcc level, and the second supply power is at a Vpp level.

Claim 5

Dependent Claim 17 words

The circuit according to claim 3 , wherein the Vpp level is greater than the Vcc level.

Claim 6

Dependent Claim 54 words

The circuit according to claim 1 , wherein the supply power selecting unit provides the first supply power of the Vcc level to the voltage control delay unit when a chip is in a stand-by mode, and provides the second supply power of the Vpp level when the chip is in an active mode.

Claim 7

Dependent Claim 25 words

The circuit according to claim 1 , wherein the power selecting signal is determined by an operational mode of the chip or an using purpose.

Claim 8

Dependent Claim 86 words

The circuit according to claim 1 , wherein the power selecting unit comprises: a D flip-flop for outputting the power selecting signal according to the first clock signal; a level shifter for converting a level of a non-inverted output from the D flip-flop; a first switch for outputting the first supply power of the Vcc level according to an output from the D flip-flop; and a second switch for outputting the second supply power of the Vpp level according to an output from the level shifter.

Claim 9

Dependent Claim 26 words

The circuit according to claim 7 , wherein the first and second switches are MOS transistors, and the first clock signal is an external clock signal.

Claim 10

Dependent Claim 19 words

The circuit according to claim 7 , wherein the level shifter converts the Vcc level to the Vpp level.

Claim 11

Dependent Claim 51 words

The circuit according to claim 1 , wherein the voltage control delay unit comprises: a plurality of inverters for sequentially delaying the first clock signal; and PMOS transistors and NMOS transistors each respectively connected to power supply terminals of the plurality of inverters and ground, and for composing a current mirror.

Claim 12

Dependent Claim 46 words

The circuit according to claim 10 , wherein the first supply power of the Vcc level or the second supply power of the Vpp level is inputted to the power supply terminals, and wells of the PMOS transistors are separated from those in the other circuit.

Claim 13

Dependent Claim 129 words

An analog delay locked loop circuit comprises: a phase detector for detecting a phase difference between an external clock signal and an internal clock signal; a charge pump for carrying out a pumping operation according to an output from the phase detector; a low pass filter for filtering an output from the charge pump, and outputting a control voltage; a multiplexer for outputting one of first to third supply power in accordance with a supply power selecting signal; and a voltage control delay unit for receiving a supply power outputted from the multiplexer, and for delaying the external clock signal according to the control voltage from the low pass filter, wherein the internal clock signal is based on the delayed external clock signal from the voltage control delay unit.

Claim 14

Dependent Claim 129 words

An analog delay locked loop circuit comprises: a phase detector for detecting a phase difference between an external clock signal and an internal clock signal; a charge pump for carrying out a pumping operation according to an output from the phase detector; a low pass filter for filtering an output from the charge pump, and outputting a control voltage; a multiplexer for outputting one of first to third supply power in accordance with a supply power selecting signal; and a voltage control delay unit for receiving a supply power outputted from the multiplexer, and for delaying the external clock signal according to the control voltage from the low pass filter, wherein the internal clock signal is based on the delayed external clock signal from the voltage control delay unit.

Claim 15

Dependent Claim 32 words

The circuit according to claim 12 , further comprising a level shifter for converting a level of an output from the voltage control delay unit, and for generating the internal clock signal.

Claim 16

Dependent Claim 39 words

The circuit according to claim 12 , wherein the first supply power is at a Vcc level, the second supply power is at a Vpp level, and the third supply power is at a voltage level lower than Vcc.

Claim 17

Dependent Claim 54 words

The circuit according to claim 12 , wherein the multiplexer outputs the second supply power of the Vpp level in order to improve a jitter property, and outputs the first or third supply power in order to reduce current consumption, the third supply power being at a lower level than the first supply power.

Claim 18

Dependent Claim 51 words

The circuit according to claim 12 , wherein the voltage control delay unit comprises: a plurality of inverters for sequentially delaying the first clock signal; and PMOS transistors and NMOS transistors each respectively connected to power supply terminals of the plurality of inverters and ground, and for composing a current mirror.

Claim 19

Dependent Claim 37 words

The circuit according to claim 16 , wherein one of the first to third supply power is inputted to the power supply terminals, and wells of the PMOS transistors are separated from those in the other circuit.

Claim 20

Dependent Claim 38 words

The circuit according to claim 17 , wherein the first supply power is at a Vcc level, the second supply power is at a Vpp level, and the third supply power is at a lower level than Vcc.

Claim 21

Dependent Claim 142 words

An analog delay locked loop circuit comprising: a phase detector that detects a phase difference between a first clock signal and a fed-back second clock signal; a control unit that outputs a control voltage according to an output from the phase detector; a supply power selector that selectively outputs a first supply power that determines a first delay range and a second supply power that determines a second delay range responsive to a supply power selecting signal; a voltage control delay unit that receives a supply power selected in the supply power selecting unit and delays the first clock signal within a corresponding selected one of the first and second delay ranges in accordance with the control voltage from the low pass filter; and a driver that receives an output from the voltage control delay unit, and generates the second clock signal.

Claim 22

Dependent Claim 142 words

An analog delay locked loop circuit comprising: a phase detector that detects a phase difference between a first clock signal and a fed-back second clock signal; a control unit that outputs a control voltage according to an output from the phase detector; a supply power selector that selectively outputs a first supply power that determines a first delay range and a second supply power that determines a second delay range responsive to a supply power selecting signal; a voltage control delay unit that receives a supply power selected in the supply power selecting unit and delays the first clock signal within a corresponding selected one of the first and second delay ranges in accordance with the control voltage from the low pass filter; and a driver that receives an output from the voltage control delay unit, and generates the second clock signal.

Claim 23

Dependent Claim 40 words

The circuit according to claim 19 , wherein the power selecting signal is determined by an operational mode of the chip or an using purpose, and wherein Vpp level is one of greater than and less than a Vcc level.

Claim 24

Dependent Claim 27 words

The circuit according to claim 19 , wherein the first supply power is at a Vcc level, and the second supply power is at a Vpp level.

Claim 25

Dependent Claim 59 words

The circuit according to claim 21 , wherein the control unit comprises: a charge pump that performs a pumping operation according to the output from the phase detector; and a filter that filters an output from the charge pump to output the control voltage, wherein the Vpp level is one of greater than and less than the Vcc level.

Claim 26

Dependent Claim 37 words

The circuit of claim 19 , wherein each of the delay ranges is determined by an operational property curve of delay variations of a delay cell in the voltage control delay unit relative to the control voltage.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2004-08-13	2005-02-12	2005-08-14	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2008-08-13	2009-02-12	2009-08-14	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2012-08-13	2013-02-12	2013-08-14	$7700.00	Window Closed / Lapsed

Analog delay locked loop circuit

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