Patent US6985401B2 successfully refreshed from Google Patents.
US6985401B2
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US
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Memory device having delay locked loop
Assignee: SK Hynix Inc
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Filing: 2004-06-01
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Granted: 2006-01-10
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Expires: 2024-06-01
Abstract
Abstract A memory device minimizes the skew between an external clock and a DQS (or DQ) after the locking state by regulating a delay ratio of a replica delay model to compensate errors of process, temperature or voltage change. The memory device comprises: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer. Here, the DLL comprises a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to a plurality of control signals inputted externally in a test mode.
Inventors
- 👤 Eun Jung Jang
- 👤 Hyung Dong Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:04
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; F; F15; F15B; F15B15/00; F15B15/20; F15B15/26; F15B15/261; G11C29/00; G11C29/02; G11C29/023; G11C29/028; G11C29/04; G11C29/50; G11C29/50012; G11C7/00; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; F15B2211/00; F15B2211/70; F15B2211/705; F15B2211/7051; F15B2211/72
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
190 words
A memory device comprising: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer, wherein the DLL comprises: a delay line for delaying a phase of the internal clock; a phase detector for comparing a phase of the internal clock with that of a feedback clock fed back through an internal circuit; a delay line controller for regulating a delay ratio to delay the internal clock in response to a phase detecting signal outputted from the phase detector; and a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to a plurality of control signals inputted externally in a test mode.
Claim 2
Dependent Claim
190 words
A memory device comprising: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer, wherein the DLL comprises: a delay line for delaying a phase of the internal clock; a phase detector for comparing a phase of the internal clock with that of a feedback clock fed back through an internal circuit; a delay line controller for regulating a delay ratio to delay the internal clock in response to a phase detecting signal outputted from the phase detector; and a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to a plurality of control signals inputted externally in a test mode.
Claim 3
Dependent Claim
69 words
The device according to claim 1 , wherein the replica delay model comprises: a plurality of delay paths having a different delay ratio respectively and for delaying an output clock outputted from the DLL; a delay regulating unit for selecting one of the plurality of delay paths by the control signals; and a delay unit for delaying a clock outputted from the delay regulating unit for a predetermined time.
Claim 4
Dependent Claim
31 words
The device according to claim 2 , wherein the delay regulating unit further comprises a setting unit for generating a plurality of delay setting data in response to the control signals.
Claim 5
Dependent Claim
37 words
The device according to claim 3 , wherein the setting unit comprises a plurality of unit shift units having a ring structure and for outputting the plurality of delay setting data in response to the control signals.
Claim 6
Dependent Claim
82 words
The device according to claim 4 , wherein the unit shift unit comprises: a first transmission unit for selectively transmitting a signal inputted through an input terminal in response to the control signal; a first latch unit for latching a signal transmitted by the first transmission unit; a second transmission unit for selectively transmitting a signal latched in the latch unit in response to the control signal; and a second latch unit for latching a signal transmitted by the second transmission unit.
Claim 7
Dependent Claim
18 words
The device according to claim 5 , wherein the second latch unit is initialized by the control signal.
Claim 8
Dependent Claim
37 words
The device according to claim 3 , wherein the delay regulating unit further comprises a plurality of selecting units for selecting one of the plurality of delay paths in response to the plurality of delay setting data.
Claim 9
Dependent Claim
28 words
The device according to claim 7 , wherein the plurality of selecting units comprise a plurality of transmission units controlled by the delay setting data one by one.
Claim 10
Dependent Claim
94 words
The device according to claim 4 , wherein the unit shift unit comprises: a first transmission unit for selectively transmitting a signal inputted through an input terminal in response to the output signal from the replica delay model controller; a first latch unit for latching a signal transmitted by the first transmission unit; a second transmission unit for selectively transmitting a signal latched in the latch unit in response to the output signal from the replica delay mode controller; and a second latch unit for latching a signal transmitted by the second transmission unit.
Claim 11
Dependent Claim
35 words
The device according to claim 9 , wherein the second latch unit is initialized by a synchronization state signal outputted from the delay line controller if a synchronization state is set by the phase detector.
Claim 12
Dependent Claim
212 words
A memory device comprising: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer, wherein the DLL comprises: a delay line for delaying a phase of the internal clock; a first phase detector for comparing a phase of the internal clock with that of a feedback clock fed back through an internal circuit; a delay line controller for regulating a delay ratio to delay the internal clock in response to a phase detecting signal outputted from the phase detector; a replica delay model controller for comparing a phase of the external clock with that of the DQS; and a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to an output signal outputted from the replica delay model controller in a test mode.
Claim 13
Dependent Claim
212 words
A memory device comprising: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer, wherein the DLL comprises: a delay line for delaying a phase of the internal clock; a first phase detector for comparing a phase of the internal clock with that of a feedback clock fed back through an internal circuit; a delay line controller for regulating a delay ratio to delay the internal clock in response to a phase detecting signal outputted from the phase detector; a replica delay model controller for comparing a phase of the external clock with that of the DQS; and a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to an output signal outputted from the replica delay model controller in a test mode.
Claim 14
Dependent Claim
76 words
The device according to claim 11 , wherein the replica delay model comprises: a plurality of delay paths having a different delay ratio each other and for delaying an output clock outputted from the DLL; a delay regulating unit for selecting one of the plurality of delay paths by an output signal from the replica delay mode controller; and a delay unit for delaying a clock outputted from the delay regulating unit for a predetermined time.
Claim 15
Dependent Claim
37 words
The device according to claim 12 , wherein the delay regulating unit further comprises a setting unit for generating a plurality of delay setting data in response to the output signal from the replica delay model controller.
Claim 16
Dependent Claim
43 words
The device according to claim 13 , wherein the setting unit comprises a plurality of unit shift units having a ring structure and for outputting the plurality of delay setting data in response to the output signal from the replica delay mode controller.
Claim 17
Dependent Claim
37 words
The device according to claim 13 , wherein the delay regulating unit further comprises a plurality of selecting units for selecting one of the plurality of delay paths in response to the plurality of delay setting data.
Claim 18
Dependent Claim
28 words
The device according to claim 15 , wherein the plurality of selecting units comprises a plurality of transmission units controlled by the delay setting data one by one.
Claim 19
Dependent Claim
58 words
The device according to claim 13 , wherein the replica delay model controller comprises: a second phase detector for comparing a phase of the external clock with that of the DQS; and a control signal generator for generating a clock synchronized with respect to the external clock in response to an output signal from the second phase detector.
Claim 20
Dependent Claim
23 words
The device according to claim 17 , wherein the second phase detector is enabled by an auto refresh command or a read command.
Claim 21
Dependent Claim
23 words
The device according to claim 17 , wherein the control signal generator is initialized when the delay setting data has the maximum value.
Claim 22
Dependent Claim
18 words
The device according to claim 11 , wherein the output controller is enabled by an auto refresh command.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-01-09 | 2009-07-11 | 2010-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-01-09 | 2013-07-11 | 2014-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-01-09 | 2017-07-11 | 2018-01-10 | $7700.00 | Window Closed / Lapsed |