Delay locked loop DLL in semiconductor device

Claim 2

A semiconductor device comprising a DLL circuit for generating an internal clock signal by receiving an external clock signal, wherein the DLL circuit includes: a delay model for modeling delay time of the internal clock signal delayed from the external clock signal; and a power supply for adjusting a core voltage by an input output voltage and supplying the adjusted voltage to the delay model.

Claim 3

The semiconductor device as recited in claim 1 , wherein the power supply includes: a noise filter for filtering a noise of the I/O voltage; and a voltage adjusting unit for adjusting the core voltage by the noise-filtered I/O voltage as a reference voltage.

Claim 4

The semiconductor device as recited in claim 2 , wherein the noise filter is a low pass filter consisting of a resistance and a capacitor.

Claim 5

The semiconductor device as recited in claim 2 , wherein the voltage adjusting unit includes: first and second NMOS transistors whose gates are coupled to the noise filter and the delay model, respectively; a third NOS transistor coupled between a common node of the first and second NMOS transistors and a ground voltage and an enable signal is applied to a gate thereof; a first PMOS transistor, which is diode-coupled, for supplying the core voltage to the second NMOS transistor; a second PMOS transistor for supplying the core voltage to the first NMOS transistor, wherein the second PMOS transistor forms a current mirror with the first PMOS transistor; and a third PMOS transistor PMOS transistor for supplying the core voltage to the delay model and a gate thereof is coupled to the first NMOS transistor.