US6724686B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
Assignee: DRAM MEMORY TECHNOLOGIES LLC
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Filing: 2003-01-10
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Granted: 2004-04-20
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Expires: 2023-01-10
Abstract
Abstract A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.
Inventors
- 👤 Tsukasa Ooishi
- 👤 Masatoshi Ishikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:33
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045; G11C7/1072
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
80 words
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a control circuit controlling operation timing of said semiconductor memory device based on an external clock signal; an interface circuit, controlled by said control circuit, receiving a control signal from the outside of said semiconductor memory device; and a transmission timing change circuit changing transmission timing of said control signal to said memory cell array according to an operation mode.
Claim 2
Dependent Claim
80 words
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a control circuit controlling operation timing of said semiconductor memory device based on an external clock signal; an interface circuit, controlled by said control circuit, receiving a control signal from the outside of said semiconductor memory device; and a transmission timing change circuit changing transmission timing of said control signal to said memory cell array according to an operation mode.
Claim 3
Dependent Claim
89 words
The semiconductor memory device according to claim 1 , wherein said transmission timing change circuit includes first and second transmission paths, said first transmission path has a first switch circuit selectively transmitting said control signal from said interface circuit to said memory cell array according to said operation mode, and said second transmission path has a latch circuit holding the level of said control signal, and a second switch circuit selectively transmitting said control signal from said latch circuit to said memory cell array according to said operation mode.
Claim 4
Dependent Claim
25 words
The semiconductor memory device according to claim 2 , wherein said control signal is an address signal specifying selected column of said memory cell array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-04-20 | 2007-10-20 | 2008-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-04-20 | 2011-10-20 | 2012-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-04-20 | 2015-10-20 | 2016-04-20 | $7700.00 | Window Closed / Lapsed |