US6011735A
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Synchronous semiconductor memory device with redundancy determination unit that can set replacement of redundant memory array provided in row and column directions
Assignee: Renesas Electronics Corp
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Filing: 1998-11-16
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Granted: 2000-01-04
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Expires: 2018-11-16
Abstract
Abstract A redundancy determination circuit receiving an address signal from an address bus outputs a replacement signal when a set address matches the received address. A multiplexer activates any spare activation signal line that activates respective redundant memory arrays provided in the row direction and column direction in a memory bank at a predetermined timing. The redundancy determination circuit can set the address to use a redundant memory array in either the row direction or the column direction. Therefore, the number of redundancy determination circuits can be reduced.
Inventors
- 👤 Tsukasa Ooishi
- 👤 Hideto Hidaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:39
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/802; G11C29/808; G11C29/816; G11C29/824
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
217 words
A synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with an external clock to input and output storage data, said synchronous semiconductor memory device comprising: a plurality of memory cell blocks each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks including a plurality of regular memory cells, a redundant memory cell row provided in a row direction, and a redundant memory cell column provided in a column direction; an address bus provided common to said plurality of memory cell blocks for transmitting a row address and a column address included in said address signal in a time-divisional manner; a plurality of selecting circuits provided corresponding to said memory cell blocks, each for selectively activating one of said redundant memory cell rows and said memory cell columns, a plurality of redundancy determination circuits provided corresponding to said memory cell blocks, each for controlling a selecting operation of said selecting circuit based on a detection of whether said address signal from said address bus indicates said row address or said column address according to said control signal and a comparison between said address signal and a preset defective address corresponding to a defective memory cell in said plurality of regular memory cells.
Claim 2
Dependent Claim
217 words
A synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with an external clock to input and output storage data, said synchronous semiconductor memory device comprising: a plurality of memory cell blocks each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks including a plurality of regular memory cells, a redundant memory cell row provided in a row direction, and a redundant memory cell column provided in a column direction; an address bus provided common to said plurality of memory cell blocks for transmitting a row address and a column address included in said address signal in a time-divisional manner; a plurality of selecting circuits provided corresponding to said memory cell blocks, each for selectively activating one of said redundant memory cell rows and said memory cell columns, a plurality of redundancy determination circuits provided corresponding to said memory cell blocks, each for controlling a selecting operation of said selecting circuit based on a detection of whether said address signal from said address bus indicates said row address or said column address according to said control signal and a comparison between said address signal and a preset defective address corresponding to a defective memory cell in said plurality of regular memory cells.
Claim 3
Dependent Claim
26 words
The synchronous semiconductor memory device according to claim 1, wherein said redundancy determination circuit and said selecting circuit are provided for each said memory cell block.
Claim 4
Dependent Claim
28 words
The synchronous semiconductor memory device according to claim 1, wherein said plurality of memory cell blocks are banks allowing a read out operation and a write operation independently.
Claim 5
Dependent Claim
93 words
The synchronous semiconductor memory device according to claim 1, wherein said address bus further transmits information specifying an activated memory cell block, said selecting circuit is provided for each said memory cell block and controlled by a replacement designating signal, and said redundancy determination circuit is provided for every pair of said memory cell blocks for outputting said replacement designating signal indicating which one of said redundant memory cell rows and said redundant memory cell columns is to be selected in said pair of memory cell blocks including said activated memory cell block.
Claim 6
Dependent Claim
63 words
The synchronous semiconductor memory device according to claim 4, wherein said redundancy determination circuit comprises a first fuse element group including a plurality of fuse elements for presetting said memory cell block corresponding to said defective address, and a second fuse element group including a plurality of fuse elements for presetting a location in said memory cell block corresponding to said defective address.
Claim 7
Dependent Claim
93 words
The synchronous semiconductor memory device according to claim 4, wherein said redundancy determination circuit comprises an address program unit including a plurality of fuse elements for presetting said defective address, and a driving circuit group for activating said replacement designating signal directed to one of said selecting circuits corresponding to said memory cell block pair, and wherein said driving circuit group includes a first driving circuit for activating said replacement designating signal, and a second driving circuit for maintaining inactive the other of said selecting circuits corresponding to said memory cell block pair.
Claim 8
Dependent Claim
143 words
The synchronous semiconductor memory device according to claim 4, wherein said redundancy determination circuit comprises an address program unit including a plurality of fuse elements for presetting said defective address, a switching circuit receiving an output of said address program unit to selectively provide the output to an internal node according to a conductive control signal, a first driving circuit for activating said replacement designating signal according to a potential of said internal node when a memory cell included in one memory cell block of said memory cell block pair is selected, and a second driving circuit for activating said replacement designating signal according to a potential of said internal node when a memory cell included in the other memory cell block of said memory cell block pair is selected, said conductive control signal being fixed so that said switch circuit is conductive.
Claim 9
Dependent Claim
184 words
A synchronous semiconductor memory device receiving an externally applied address signal and a control signal in synchronization with an external clock to input and output stored data, said synchronous semiconductor memory device comprising: a plurality of memory cell blocks, each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks including a plurality of regular memory cells, and a redundant memory cell; an address bus provided common to said plurality of memory cell blocks for transmitting a row address and a column address included in said address signal in a time-divisional manner; and a redundancy determination circuit provided common to at least two of said plurality of memory cell blocks to detect which one of the corresponding memory cell blocks incorporating an address of said regular memory cell does said address signal from said address bus correspond to according to said control signal, and activating a select operation of a redundant memory cell in said corresponding memory cell block when said address signal matches a preset defective address in said plurality of regular memory cells.
Claim 10
Dependent Claim
184 words
A synchronous semiconductor memory device receiving an externally applied address signal and a control signal in synchronization with an external clock to input and output stored data, said synchronous semiconductor memory device comprising: a plurality of memory cell blocks, each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks including a plurality of regular memory cells, and a redundant memory cell; an address bus provided common to said plurality of memory cell blocks for transmitting a row address and a column address included in said address signal in a time-divisional manner; and a redundancy determination circuit provided common to at least two of said plurality of memory cell blocks to detect which one of the corresponding memory cell blocks incorporating an address of said regular memory cell does said address signal from said address bus correspond to according to said control signal, and activating a select operation of a redundant memory cell in said corresponding memory cell block when said address signal matches a preset defective address in said plurality of regular memory cells.
Claim 11
Dependent Claim
208 words
A synchronous semiconductor memory device receiving an externally applied address signal and a control signal in synchronization with an external clock to input and output stored data, said synchronous semiconductor memory device comprising: a plurality of memory cell blocks, each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks including a plurality of regular memory cells, a redundant memory cell row provided in a row direction, and a redundant memory cell column provided in a column direction; a redundancy determination unit including a plurality of redundancy determination circuits for activating a replacement designating signal when said address signal matches a preset defective address in said plurality of regular memory cells; an encoder for encoding the replacement designating signal output from said plurality of redundancy determination circuits; a replacement designating signal bus for receiving an output of said encoder; and a plurality of decoders provided corresponding to each of said plurality of memory cell blocks for receiving and decoding the output of said encoder through said replacement designating signal bus, each of said plurality of decoders activating a select operation of any of said redundancy memory cell row and said redundant memory cell column included in each memory block.
Claim 12
Dependent Claim
208 words
A synchronous semiconductor memory device receiving an externally applied address signal and a control signal in synchronization with an external clock to input and output stored data, said synchronous semiconductor memory device comprising: a plurality of memory cell blocks, each having a plurality of memory cells arranged in rows and columns, each of said plurality of memory cell blocks including a plurality of regular memory cells, a redundant memory cell row provided in a row direction, and a redundant memory cell column provided in a column direction; a redundancy determination unit including a plurality of redundancy determination circuits for activating a replacement designating signal when said address signal matches a preset defective address in said plurality of regular memory cells; an encoder for encoding the replacement designating signal output from said plurality of redundancy determination circuits; a replacement designating signal bus for receiving an output of said encoder; and a plurality of decoders provided corresponding to each of said plurality of memory cell blocks for receiving and decoding the output of said encoder through said replacement designating signal bus, each of said plurality of decoders activating a select operation of any of said redundancy memory cell row and said redundant memory cell column included in each memory block.
Claim 13
Dependent Claim
60 words
The synchronous semiconductor memory device according to claim 9, wherein said address signal, said control signal, and said stored data are applied as a plurality of packets, said address signal includes a row address and a column address arranged in said packets in a time-divisional manner, and said redundancy determination unit sequentially compares said row address and said column address.
Claim 14
Dependent Claim
60 words
The synchronous semiconductor memory device according to claim 9, wherein said address signal, said control signal, and said stored data are applied as a plurality of packets, said address signal is divided into a plurality of address data rows arranged in said packet in a time-divisional manner, and said redundancy determination unit sequentially compares said plurality of address data rows.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-03 | 2003-07-05 | 2004-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-03 | 2007-07-05 | 2008-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-03 | 2011-07-05 | 2012-01-04 | $7700.00 | Window Closed / Lapsed |