Synchronous type semiconductor memory device which can be adapted to high frequency system clock signal

Claim 2

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; column selecting means activated at the time of activation of a column address strobe signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; data output means for sequentially providing data amplified by said plurality of data reading and amplifying means to an output buffer in synchronism with activation of said column address strobe signal; and output buffer control means responsive to any transition of said column address strobe signal from an active state to a non-active state for activating said output buffer.

Claim 3

A semiconductor memory device sequentially providing a plurality of read data from a plurality of memory cells selected simultaneously, in synchronism with a change cycle of a column address strobe signal in a predetermined operation mode, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; column selecting means responsive to a first activation transition of said column address strobe signal for simultaneously selecting a plurality of columns of said memory cell array specified by an external address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; latch means for receiving and holding outputs of said plurality of data reading and amplifying means; data output means receiving outputs of said latch means and responsive to an activation transition of said column address strobe signal for sequentially outputting said outputs of said latch means; output driving means receiving outputs of said data output means and responsive to an output buffer activation signal for externally outputting corresponding signals; and output buffer control means responsive to a first deactivation transition of said column address strobe signal for outputting said output buffer activation signal.

Claim 4

A semiconductor memory device sequentially providing a plurality of read data from a plurality of memory cells selected simultaneously, in synchronism with a change cycle of a column address strobe signal in a predetermined operation mode, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; column selecting means responsive to a first activation transition of said column address strobe signal for simultaneously selecting a plurality of columns of said memory cell array specified by an external address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; latch means for receiving and holding outputs of said plurality of data reading and amplifying means; data output means receiving outputs of said latch means and responsive to an activation transition of said column address strobe signal for sequentially outputting said outputs of said latch means; output driving means receiving outputs of said data output means and responsive to an output buffer activation signal for externally outputting corresponding signals; and output buffer control means responsive to a first deactivation transition of said column address strobe signal for outputting said output buffer activation signal.

Claim 5

The semiconductor memory device according to claim 2, wherein said first activation transition and said first deactivation transition are included in the same cycle of change of said column address strobe signal.

Claim 6

The semiconductor memory device according to claim 2, wherein said output buffer control means includes means responsive to said first deactivation transition of said column address strobe signal for outputting an active internal output control signal, and means for sensing activation of said column address strobe signal for maintaining said output buffer control signal in an active state in a period during which an external read operation control signal and said internal output control signal are both active.

Claim 7

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of a column address strobe signal; column selecting means activated at the time of activation of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal; and data input/output means for sequentially transmitting and receiving data between memory cells of a corresponding column among said plurality of columns and the outside world in synchronism with activation of said internal clock signal.

Claim 8

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of a column address strobe signal; column selecting means activated at the time of activation of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal; and data input/output means for sequentially transmitting and receiving data between memory cells of a corresponding column among said plurality of columns and the outside world in synchronism with activation of said internal clock signal.

Claim 9

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of a column address strobe signal; column selecting means activated at the time of activation of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; and output control means for sequentially outputting data amplified by said plurality of data reading and amplifying means, in synchronism with activation of said internal clock signal.

Claim 10

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of a column address strobe signal; column selecting means activated at the time of activation of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; and output control means for sequentially outputting data amplified by said plurality of data reading and amplifying means, in synchronism with activation of said internal clock signal.

Claim 11

A semiconductor memory device for sequentially outputting a plurality of read data from a plurality of memory cells selected simultaneously, in synchronism with an activation cycle of a column address strobe signal in a predetermined operation mode, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of said column address strobe signal; column selecting means responsive to a first activation transition of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array specified by an external address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; latch means for receiving and holding outputs of said plurality of data reading and amplifying means; and output control means receiving outputs of said latch means and responsive to an activation transition after said first activation transition of said internal clock signal for sequentially and externally providing said outputs of said latch means.

Claim 12

A semiconductor memory device for sequentially outputting a plurality of read data from a plurality of memory cells selected simultaneously, in synchronism with an activation cycle of a column address strobe signal in a predetermined operation mode, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of said column address strobe signal; column selecting means responsive to a first activation transition of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array specified by an external address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; latch means for receiving and holding outputs of said plurality of data reading and amplifying means; and output control means receiving outputs of said latch means and responsive to an activation transition after said first activation transition of said internal clock signal for sequentially and externally providing said outputs of said latch means.

Claim 13

The semiconductor memory device according to claim 7, wherein said synchronization signal generating means includes a logic circuit having first and second input nodes and responsive to activation of an input signal to any one of the input nodes for inverting a level of an output signal, and a delay circuit receiving said column address strobe signal for outputting the same to said first input node with a delay time corresponding to said predetermined pulse length, said column address strobe signal being applied to said second input node.

Claim 14

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of a column address strobe signal; column selecting means activated at the time of activation of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; data output means for sequentially applying data amplified by said plurality of data reading and amplifying means to an output buffer, in synchronism with activation of said internal clock signal; and output buffer control means responsive to any transition of said internal clock signal from an active state to a non-active state for activating said output buffer.

Claim 15

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of a column address strobe signal; column selecting means activated at the time of activation of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array according to a column address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; data output means for sequentially applying data amplified by said plurality of data reading and amplifying means to an output buffer, in synchronism with activation of said internal clock signal; and output buffer control means responsive to any transition of said internal clock signal from an active state to a non-active state for activating said output buffer.

Claim 16

A semiconductor memory device for sequentially outputting a plurality of read data from a plurality of memory cells selected simultaneously, in synchronism with an activation cycle of a column address strobe signal in a predetermined operation mode, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of said column address strobe signal; column selecting means responsive to a first activation transition of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array specified by an external address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; latch means for receiving and holding outputs of said plurality of data reading and amplifying means; and data output means receiving outputs of said latch means and responsive to an activation transition of said internal clock signal for sequentially providing said outputs of said latch means; output driving means receiving an output of said data output means and responsive to an output buffer activation signal for externally outputting a corresponding signal; and output buffer control means responsive to a first deactivation transition of said internal clock signal for outputting said output buffer activation signal.

Claim 17

A semiconductor memory device for sequentially outputting a plurality of read data from a plurality of memory cells selected simultaneously, in synchronism with an activation cycle of a column address strobe signal in a predetermined operation mode, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; synchronization signal generating means for generating an internal clock signal having a predetermined pulse length in synchronism with an activation transition of said column address strobe signal; column selecting means responsive to a first activation transition of said internal clock signal for simultaneously selecting a plurality of columns of said memory cell array specified by an external address signal; a plurality of data reading and amplifying means each for amplifying data of a memory cell of a corresponding column among said plurality of columns; latch means for receiving and holding outputs of said plurality of data reading and amplifying means; and data output means receiving outputs of said latch means and responsive to an activation transition of said internal clock signal for sequentially providing said outputs of said latch means; output driving means receiving an output of said data output means and responsive to an output buffer activation signal for externally outputting a corresponding signal; and output buffer control means responsive to a first deactivation transition of said internal clock signal for outputting said output buffer activation signal.

Claim 18

The semiconductor memory device according to claim 10, wherein said first activation transition and said first deactivation transition are included in the same cycle of change of said column address strobe signal.