Multi-level symmetrical inductor

Claim 2

An inductor made by integrated circuit technology comprising: a substrate; a first insulation layer formed on the substrate; a second insulation layer formed adjacent to the first insulation layer; a first conductive section formed in a first layer located on a first side of a first line; a second conductive section formed in the first layer located on a second side of the first line, the first conductive section and the second conductive section being symmetrical with respect to the first line; a third conductive section formed in a second layer located on the first side of the first line; a fourth conductive section formed in the second layer located on the second side of the first line, the third conductive section and the fourth conductive section being symmetrical with respect to the first line; wherein a first end of the first conductive section is connected to a first end of the fourth conductive section with a first via plug, and a first end of the second conductive section is connected to a first end of the third conductive section with a second via plug.

Claim 3

The inductor of claim 1 further comprising: a fifth conductive section formed in the second layer located on the first side of the first line; a sixth conductive section formed in the second layer located on the second side of the first line, the fifth conductive section and the sixth conductive section being symmetrical with respect to the first line; and a first connecting conductive section formed in the first layer, a first end of the first connecting conductive section connected to a second end of the third conductive section with a third via plug, a second end of the first connecting conductive section connected to a first end of the sixth conductive section with a fourth via plug; wherein a first end of the fifth conductive section is connected directly to a second end of the fourth conductive section in the second layer.

Claim 4

The inductor of claim 1 further comprising: a seventh conductive section formed in the first layer located on the first side of the first line; a eighth conductive section formed in the first layer located on the second side of the first line, the seventh conductive section and the eighth conductive section being symmetrical with respect to the first line; and a second connecting conductive section formed in the second layer, a first end of the second connecting conductive section connected to a first end of the seventh conductive section with a fifth via plug, a second end of the second connecting conductive section connected to a second end of the second conductive section with a sixth via plug; wherein a first end of the eighth conductive section is connected directly to a second end of the first conductive section in the first layer.

Claim 5

An integrated circuit inductor comprising: at least two stacked planar inductor layers ranging from a top layer to a bottom layer, the top layer being odd and the remaining layers consecutively alternating between even and odd, each layer comprising: a right spiral inductor having an outer end and an inner end; and a left spiral inductor having an outer end and an inner end, the left spiral inductor substantially mirror symmetric to the right spiral inductor in the layer and offset from the right spiral inductor in the layer; wherein both the right and left spiral inductors are disposed in the layer except for regions where the first right and left spiral inductors overlap, in which a part of one of the right or left spiral inductors is disposed in an adjacent layer; wherein the outer ends in the top layer are separate input or output ends of the integrated circuit inductor; wherein the bottom layer, when even, has outer ends of the left and right spiral indictors mutually connected, and when odd, has inner ends of the left and right spiral indictors mutually connected; and wherein for each layer except the bottom layer, when odd, the inner end of the right spiral inductor is connected to the inner end of the left spiral inductor of the next lower layer and the inner end of the left spiral inductor is connected to the inner end of the right spiral inductor of the next lower layer, and when even, the outer end of the right spiral inductor is connected to the outer end of the left spiral inductor of the next lower layer and the Outer end of the left spiral inductor is connected to the outer end of the right spiral inductor of the next lower layer.

Claim 6

An integrated circuit inductor comprising: at least two stacked planar inductor layers ranging from a top layer to a bottom layer, the top layer being odd and the remaining layers consecutively alternating between even and odd, each layer comprising: a right spiral inductor having an outer end and an inner end; and a left spiral inductor having an outer end and an inner end, the left spiral inductor substantially mirror symmetric to the right spiral inductor in the layer and offset from the right spiral inductor in the layer; wherein both the right and left spiral inductors are disposed in the layer except for regions where the first right and left spiral inductors overlap, in which a part of one of the right or left spiral inductors is disposed in an adjacent layer; wherein the outer ends in the top layer are separate input or output ends of the integrated circuit inductor; wherein the bottom layer, when even, has outer ends of the left and right spiral indictors mutually connected, and when odd, has inner ends of the left and right spiral indictors mutually connected; and wherein for each layer except the bottom layer, when odd, the inner end of the right spiral inductor is connected to the inner end of the left spiral inductor of the next lower layer and the inner end of the left spiral inductor is connected to the inner end of the right spiral inductor of the next lower layer, and when even, the outer end of the right spiral inductor is connected to the outer end of the left spiral inductor of the next lower layer and the Outer end of the left spiral inductor is connected to the outer end of the right spiral inductor of the next lower layer.

Claim 7

The integrated circuit inductor of claim 4 , wherein for regions where the first right and left spiral inductors overlap, the adjacent layer to an odd layer is the next lower layer, and the adjacent layer to an even layer is the next upper layer.

Claim 8

The integrated circuit inductor of claim 5 , wherein in a layer, the offset for the left spiral inductor from the right spiral inductor is in a direction substantially perpendicular to a line between the outer and inner ends of the right spiral inductor.