US6950487B2
Expired / Lapsed
US
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Phase splitter using digital delay locked loops
Assignee: Round Rock Research LLC
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Filing: 2001-05-18
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Granted: 2005-09-27
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Expires: 2021-05-18
Abstract
Abstract A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.
Inventors
- 👤 Feng Lin
- 👤 R. Jacob Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:54
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03K; H03K5/00; H03K5/15; H03K5/15013; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/0818; H03L7/085; H03L7/087; H03L7/089
Claims Analysis
Total Claims: 74
Claim 1
Independent Claim
160 words
A digital phase splitter comprising: a first forward path to delay a first input clock signal by a first amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by a second amount of delay to produce third and fourth output clock signals, wherein the second input clock signal is unrelated to the first and second output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the first amount of delay the second amount of delay such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.
Claim 2
Dependent Claim
160 words
A digital phase splitter comprising: a first forward path to delay a first input clock signal by a first amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by a second amount of delay to produce third and fourth output clock signals, wherein the second input clock signal is unrelated to the first and second output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the first amount of delay the second amount of delay such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.
Claim 3
Dependent Claim
154 words
A digital phase splitter comprising: a first forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals; a feedback path connected one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 80, 270 and 360 degrees out of phase with the first input clock signal, wherein the first and second input clock signals are complementary signals.
Claim 4
Dependent Claim
154 words
A digital phase splitter comprising: a first forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals; a feedback path connected one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 80, 270 and 360 degrees out of phase with the first input clock signal, wherein the first and second input clock signals are complementary signals.
Claim 5
Dependent Claim
153 words
A digital phase splitter comprising: a first forward path to delay first input clock signal by an amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 80, 270 and 360 degrees out of phase with the first input clock signal, wherein the feedback signal is the fourth output clock signal.
Claim 6
Dependent Claim
153 words
A digital phase splitter comprising: a first forward path to delay first input clock signal by an amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 80, 270 and 360 degrees out of phase with the first input clock signal, wherein the feedback signal is the fourth output clock signal.
Claim 7
Dependent Claim
151 words
A digital phase splitter comprising: a first forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 80, 270 and 360 degrees out of phase with the first input clock signal, wherein the controller includes a shift register.
Claim 8
Dependent Claim
151 words
A digital phase splitter comprising: a first forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 80, 270 and 360 degrees out of phase with the first input clock signal, wherein the controller includes a shift register.
Claim 9
Dependent Claim
33 words
The phase splitter of claim 1 , wherein each of the first and second forward path includes first and second delay lines, each of the delay lines including a plurality of delay stages.
Claim 10
Dependent Claim
194 words
A digital phase splitter comprising: a first forward path to delay first input clock signal by an amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 80, 270 and 360 degrees out of phase with the first input clock signal wherein each of the first and second forward path includes first and second delay lines, each of the delay lines including a plurality of delay stages, and wherein a delay resolution of the phase splitter is equal to two delay stages when the feedback and first input clock signals are synchronized.
Claim 11
Dependent Claim
194 words
A digital phase splitter comprising: a first forward path to delay first input clock signal by an amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by the same amount of delay to produce third and fourth output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the amount of delay of the first and second forward paths such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 80, 270 and 360 degrees out of phase with the first input clock signal wherein each of the first and second forward path includes first and second delay lines, each of the delay lines including a plurality of delay stages, and wherein a delay resolution of the phase splitter is equal to two delay stages when the feedback and first input clock signals are synchronized.
Claim 12
Dependent Claim
17 words
The phase splitter of claim 6 , wherein each of the delay stages includes one delay element.
Claim 13
Dependent Claim
14 words
The phase splitter of claim 7 , wherein the delay element is an invertor.
Claim 14
Dependent Claim
216 words
A digital phase splitter comprising: a first delay line to apply amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply a second amount of delay to the first output clock sign to produce a second output clock signal; a third delay line to apply a third amount of delay to a second input clock signal to produce a third output clock signal, wherein the second input clock signal is unrelated to the first and second output clock signals; a fourth delay line connected to the third delay line to apply a fourth amount of delay to the third output clock sign to produce a fourth output clock signal; a feedback path connected to one of the delay lines to produce a feedback signal; a phase detector to provide shifting signals based on a difference between phases of the feedback and first input clock signals; and a controller to adjust the amount of delay applied to all of the delay lines such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are one fourth, one-half, three-fourths and one clock cycle delayed from the first input clock signal.
Claim 15
Dependent Claim
216 words
A digital phase splitter comprising: a first delay line to apply amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply a second amount of delay to the first output clock sign to produce a second output clock signal; a third delay line to apply a third amount of delay to a second input clock signal to produce a third output clock signal, wherein the second input clock signal is unrelated to the first and second output clock signals; a fourth delay line connected to the third delay line to apply a fourth amount of delay to the third output clock sign to produce a fourth output clock signal; a feedback path connected to one of the delay lines to produce a feedback signal; a phase detector to provide shifting signals based on a difference between phases of the feedback and first input clock signals; and a controller to adjust the amount of delay applied to all of the delay lines such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are one fourth, one-half, three-fourths and one clock cycle delayed from the first input clock signal.
Claim 16
Dependent Claim
214 words
A digital phase splitter comprising: a first delay line to apply an amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal; a third delay line to apply the same amount of delay to a second input clock signal to produce a third output clock signal; a fourth delay line connected to the third delay line to apply the same amount of delay to the third output clock signal to produce a fourth output clock signal; a feedback path connected to one of the delay lines to produce a feedback signal; a phase detector to provide shifting signals based on a difference between phases of the feedback and first input clock signals; and a controller to adjust the amount of delay applied to all of the delay lines such that when the feedback and first input clock signals are synchronized the first, second, third and fourth output clock signals are one fourth, one-half, three-fourths and one clock cycle delayed from the first input clock signal, wherein second input clock signal is an inverse of the first clock signal.
Claim 17
Dependent Claim
214 words
A digital phase splitter comprising: a first delay line to apply an amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal; a third delay line to apply the same amount of delay to a second input clock signal to produce a third output clock signal; a fourth delay line connected to the third delay line to apply the same amount of delay to the third output clock signal to produce a fourth output clock signal; a feedback path connected to one of the delay lines to produce a feedback signal; a phase detector to provide shifting signals based on a difference between phases of the feedback and first input clock signals; and a controller to adjust the amount of delay applied to all of the delay lines such that when the feedback and first input clock signals are synchronized the first, second, third and fourth output clock signals are one fourth, one-half, three-fourths and one clock cycle delayed from the first input clock signal, wherein second input clock signal is an inverse of the first clock signal.
Claim 18
Dependent Claim
19 words
The phase splitter of claim 9 , wherein each of the delay lines includes a plurality of delay stages.
Claim 19
Dependent Claim
228 words
A digital phase splitter comprising: a first delay line to apply an amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal; a third delay line to apply the same amount of delay to a second input clock signal to produce a third output clock signal; a fourth delay line connected to the third delay line to apply the same amount of delay to the third output clock signal to produce a fourth output clock signal; a feedback path connected to one of the delay lines to produce a feedback signal; a phase detector to provide shifting signals based on a difference between phases of the feedback and first input clock signals; and a controller to adjust the amount of delay applied to all of the delay lines such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are one fourth, one-half, three-fourths and one clock cycle delayed from the first input clock signal, wherein each of the delay lines includes a plurality of delay stages, and wherein a delay resolution of the phase splitter is equal to two delay stages.
Claim 20
Dependent Claim
228 words
A digital phase splitter comprising: a first delay line to apply an amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal; a third delay line to apply the same amount of delay to a second input clock signal to produce a third output clock signal; a fourth delay line connected to the third delay line to apply the same amount of delay to the third output clock signal to produce a fourth output clock signal; a feedback path connected to one of the delay lines to produce a feedback signal; a phase detector to provide shifting signals based on a difference between phases of the feedback and first input clock signals; and a controller to adjust the amount of delay applied to all of the delay lines such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are one fourth, one-half, three-fourths and one clock cycle delayed from the first input clock signal, wherein each of the delay lines includes a plurality of delay stages, and wherein a delay resolution of the phase splitter is equal to two delay stages.
Claim 21
Dependent Claim
17 words
The phase splitter of claim 12 , wherein each of the delay stages includes one delay element.
Claim 22
Dependent Claim
14 words
The phase splitter of claim 13 , wherein the delay element is an invertor.
Claim 23
Dependent Claim
110 words
A digital phase splitter comprising: a forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals; a feedback path connected the forward path to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback signal and a second input clock signal; and a controller to adjust the amount of delay of the forward paths such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are 90 and 180 degrees out of phase with the first input clock signal.
Claim 24
Dependent Claim
110 words
A digital phase splitter comprising: a forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals; a feedback path connected the forward path to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback signal and a second input clock signal; and a controller to adjust the amount of delay of the forward paths such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are 90 and 180 degrees out of phase with the first input clock signal.
Claim 25
Dependent Claim
18 words
The phase splitter of claim 15 , wherein the first and second input clock signals are complementary signals.
Claim 26
Dependent Claim
17 words
The phase splitter of claim 15 , wherein the feedback signal is the second output clock signal.
Claim 27
Dependent Claim
20 words
The phase splitter of claim 17 , wherein a delay resolution of the phase splitter is equal to 200 picoseconds.
Claim 28
Dependent Claim
28 words
The phase splitter of claim 15 , wherein the forward path includes first and second delay lines, each of the delay lines including a plurality of delay stages.
Claim 29
Dependent Claim
21 words
The phase splitter of claim 19 , wherein a delay resolution of the phase splitter is equal to two delay stages.
Claim 30
Dependent Claim
17 words
The phase splitter of claim 20 , wherein each of the delay stages includes one delay element.
Claim 31
Dependent Claim
14 words
The phase splitter of claim 21 , wherein the delay element is an invertor.
Claim 32
Dependent Claim
143 words
A digital phase splitter comprising: a first delay line to apply amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal; a feedback path connected to the second delay line to produce a feedback signal; a phase detector to provide shifting signals based on a difference between phases of the feedback signal and a second input clock signal; and a controller to adjust the amount of delay applied to the first and second delay lines such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are one-fourth and one-half clock cycle delayed from the first input clock signal.
Claim 33
Dependent Claim
143 words
A digital phase splitter comprising: a first delay line to apply amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal; a feedback path connected to the second delay line to produce a feedback signal; a phase detector to provide shifting signals based on a difference between phases of the feedback signal and a second input clock signal; and a controller to adjust the amount of delay applied to the first and second delay lines such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are one-fourth and one-half clock cycle delayed from the first input clock signal.
Claim 34
Dependent Claim
19 words
The phase splitter of claim 23 , wherein second clock signal is an inverse of the first clock signal.
Claim 35
Dependent Claim
21 words
The phase splitter of claim 24 , wherein a delay resolution of the phase splitter is equal to two delay stages.
Claim 36
Dependent Claim
17 words
The phase splitter of claim 25 , wherein each of the delay stages includes one delay element.
Claim 37
Dependent Claim
14 words
The phase splitter of claim 26 , wherein the delay element is an invertor.
Claim 38
Dependent Claim
144 words
A digital phase splitter comprising: a forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals; a feedback path connected the forward path to produce a feedback signal; a first phase detector to provide a first set of shifting signals based on a difference between the phases of the feedback signal and a second input clock signal; a second phase detector to provide a second set of shifting signals based on a difference between the phases of the feedback signal and the second input clock signal; and a controller to adjust the amount of delay of the forward path such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are 90 and 180 degrees out of phase with the first input clock signal.
Claim 39
Dependent Claim
144 words
A digital phase splitter comprising: a forward path to delay a first input clock signal by an amount of delay to produce first and second output clock signals; a feedback path connected the forward path to produce a feedback signal; a first phase detector to provide a first set of shifting signals based on a difference between the phases of the feedback signal and a second input clock signal; a second phase detector to provide a second set of shifting signals based on a difference between the phases of the feedback signal and the second input clock signal; and a controller to adjust the amount of delay of the forward path such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are 90 and 180 degrees out of phase with the first input clock signal.
Claim 40
Dependent Claim
18 words
The phase splitter of claim 28 , wherein the first and second input clock signals are complementary signals.
Claim 41
Dependent Claim
17 words
The phase splitter of claim 28 , wherein the feedback signal is the second output clock signal.
Claim 42
Dependent Claim
68 words
The phase splitter of claim 28 , wherein the forward path includes first and second delay lines, each of the delay lines including: a coarse delay segment including a plurality of coarse delay stages; and a fine delay segment including a plurality of fine delay stages, wherein a delay of each of the fine delay stages is smaller than a delay of each of the coarse delay stages.
Claim 43
Dependent Claim
25 words
The phase splitter of claim 31 , wherein a delay resolution of the phase splitter is equal to two coarse and two fine delay stages.
Claim 44
Dependent Claim
18 words
The phase splitter of claim 32 , wherein each of the coarse delay stages includes one delay element.
Claim 45
Dependent Claim
14 words
The phase splitter of claim 33 , wherein the delay element is an invertor.
Claim 46
Dependent Claim
35 words
The phase splitter of claim 32 , wherein a delay of each of the coarse delay stages is about 100 picoseconds, and a delay of each of the fine delay stages is about 30 picoseconds.
Claim 47
Dependent Claim
176 words
A digital phase splitter comprising: a first delay line to apply an amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal; a feedback path connected to the second delay line to produce a feedback signal; a first phase detector to provide a first set of shifting signals based on a difference between the phases of the feedback signal and a second input clock signal; a second phase detector to provide a second set of shifting signals based on a difference between the phases of the feedback signal and the second input clock signal; and a controller to adjust the amount of delay of the forward path such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are 90 and 180 degrees out of phase with the first input clock signal.
Claim 48
Dependent Claim
176 words
A digital phase splitter comprising: a first delay line to apply an amount of delay to a first input clock signal to produce a first output clock signal; a second delay line connected to the first delay line to apply the same amount of delay to the first output clock signal to produce a second output clock signal; a feedback path connected to the second delay line to produce a feedback signal; a first phase detector to provide a first set of shifting signals based on a difference between the phases of the feedback signal and a second input clock signal; a second phase detector to provide a second set of shifting signals based on a difference between the phases of the feedback signal and the second input clock signal; and a controller to adjust the amount of delay of the forward path such that when the feedback and second input clock signals are synchronized, the first and second output clock signals are 90 and 180 degrees out of phase with the first input clock signal.
Claim 49
Dependent Claim
18 words
The phase splitter of claim 36 , wherein the first and second input clock signals are complementary signals.
Claim 50
Dependent Claim
17 words
The phase splitter of claim 36 , wherein the feedback signal is the second output clock signal.
Claim 51
Dependent Claim
62 words
The phase splitter of claim 36 , wherein each of the first and second delay lines includes: a coarse delay segment including a plurality of coarse delay stages; and a fine delay segment including a plurality of fine delay stages, wherein a delay of each of the fine delay stages is smaller th a delay of each of the coarse delay stages.
Claim 52
Dependent Claim
25 words
The phase splitter of claim 39 , wherein a delay resolution of the phase splitter is equal to two coarse and two fine delay stages.
Claim 53
Dependent Claim
18 words
The phase splitter of claim 40 , wherein each of the coarse delay stages includes one delay element.
Claim 54
Dependent Claim
14 words
The phase splitter of claim 41 , wherein the delay element is an invertor.
Claim 55
Dependent Claim
35 words
The phase splitter of claim 40 , wherein a delay of each of the coarse delay stages is about 100 picoseconds and a delay of each of the fine delay stages is about 30 picoseconds.
Claim 56
Dependent Claim
191 words
A memory device comprising: memory cells; a capture circuit; and a phase splitter connected to provide a clock signal to the capture circuit to capture a data signal from the memory cells, the phase splitter comprising: a first forward path delay a first input clock signal by a first amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by a second amount of delay to produce third and fourth output clock signals, wherein the second input clock signal is unrelated to the first and second output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the first amount of delay and the second amount of delay such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.
Claim 57
Dependent Claim
191 words
A memory device comprising: memory cells; a capture circuit; and a phase splitter connected to provide a clock signal to the capture circuit to capture a data signal from the memory cells, the phase splitter comprising: a first forward path delay a first input clock signal by a first amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by a second amount of delay to produce third and fourth output clock signals, wherein the second input clock signal is unrelated to the first and second output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the first amount of delay and the second amount of delay such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.
Claim 58
Independent Claim
188 words
A system comprising: a processor; a memory device; and a controller connected between the processor and the memory device, the controller having a phase splitter to generate multiple signals, the phase splitter comprising: a first forward path delay a first input clock signal by a first amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by a second amount of delay to produce third and fourth output clock signals, wherein the second input clock signal is unrelated to the first and second output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the first amount of delay and the second amount o delay such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.
Claim 59
Independent Claim
188 words
A system comprising: a processor; a memory device; and a controller connected between the processor and the memory device, the controller having a phase splitter to generate multiple signals, the phase splitter comprising: a first forward path delay a first input clock signal by a first amount of delay to produce first and second output clock signals; a second forward path to delay a second input clock signal by a second amount of delay to produce third and fourth output clock signals, wherein the second input clock signal is unrelated to the first and second output clock signals; a feedback path connected to one of the forward paths to produce a feedback signal; a phase detector to provide shifting signals based on a difference between the phases of the feedback and first input clock signals; and a controller to adjust the first amount of delay and the second amount o delay such that when the feedback and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.
Claim 60
Independent Claim
138 words
A method of generating multiple clock signals, the method comprising: delaying a first clock signal with a first amount of delay to generate first and second output clock signals; delaying a second clock signal with a second amount of delay to generate third and fourth output clock signals, wherein the second clock signal is unrelated to the first and second output clock signals; generating a feedback signal from the fourth output clock signal; generating shifting signals based on a difference between the phases of the feedback and first clock signals; and adjusting the amount of delay of the first and second forward paths such that when the feedback and first clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first clock signal.
Claim 61
Independent Claim
138 words
A method of generating multiple clock signals, the method comprising: delaying a first clock signal with a first amount of delay to generate first and second output clock signals; delaying a second clock signal with a second amount of delay to generate third and fourth output clock signals, wherein the second clock signal is unrelated to the first and second output clock signals; generating a feedback signal from the fourth output clock signal; generating shifting signals based on a difference between the phases of the feedback and first clock signals; and adjusting the amount of delay of the first and second forward paths such that when the feedback and first clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first clock signal.
Claim 62
Dependent Claim
49 words
The method of claim 46 , wherein delaying the first clock signal includes: propagating the first clock signal through a first delay line to generate the first output clock signal; and propagating the first output clock signal through a second delay line to generate the second output clock signal.
Claim 63
Dependent Claim
40 words
The method of claim 47 , wherein propagating each of the first clock signal and the first output clock signal includes propagating each signal through a plurality of delay stages, herein each of the delay stages includes one delay element.
Claim 64
Dependent Claim
50 words
The method of claim 46 , wherein delaying the second clock signal includes: propagating the second input clock signal through a first delay line to generate the third output clock signal; and propagating the third output clock signal through a second delay line to generate the fourth output clock signal.
Claim 65
Dependent Claim
40 words
The method of claim 49 , wherein propagating each of the second clock signal and the third output clock signal includes propagating each signal through a plurality of delay stages herein each of the delay stages includes one delay element.
Claim 66
Independent Claim
186 words
A method of generating multiple clock signals, the method comprising: receiving first and second input clock signals; propagating the first input clock signal through a number of delay stages of a first delay line to generate a first output clock signal; propagating the first output clock signal through the same number of delay stages of a second delay line to generate a second output clock signal; propagating the second input clock signal through the same number of delay stages of a third delay line to generate a third output clock signal; propagating the third output clock signal through the same number of delay stages of a fourth delay line to generate a fourth output clock signal; comparing a phase difference between the fourth output clock and first input clock signals to determine to provide shifting signals; and adjusting the amount of delay based on the shifting signals such that when the fourth output clock and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.
Claim 67
Independent Claim
186 words
A method of generating multiple clock signals, the method comprising: receiving first and second input clock signals; propagating the first input clock signal through a number of delay stages of a first delay line to generate a first output clock signal; propagating the first output clock signal through the same number of delay stages of a second delay line to generate a second output clock signal; propagating the second input clock signal through the same number of delay stages of a third delay line to generate a third output clock signal; propagating the third output clock signal through the same number of delay stages of a fourth delay line to generate a fourth output clock signal; comparing a phase difference between the fourth output clock and first input clock signals to determine to provide shifting signals; and adjusting the amount of delay based on the shifting signals such that when the fourth output clock and first input clock signals are synchronized, the first, second, third and fourth output clock signals are 90, 180, 270 and 360 degrees out of phase with the first input clock signal.
Claim 68
Independent Claim
79 words
A method of generating multiple clock signals, the method comprising: delaying a first input clock signal to generate a first output clock signal; delaying the first output clock signal to generate a second output clock signal; generating a feedback signal from the second output clock signal; and synchronizing the feedback signal and a second input clock signal such that the first and second output clock signals are one-fourth and one-half clock cycle delayed from the first input clock signal.
Claim 69
Independent Claim
79 words
A method of generating multiple clock signals, the method comprising: delaying a first input clock signal to generate a first output clock signal; delaying the first output clock signal to generate a second output clock signal; generating a feedback signal from the second output clock signal; and synchronizing the feedback signal and a second input clock signal such that the first and second output clock signals are one-fourth and one-half clock cycle delayed from the first input clock signal.
Claim 70
Dependent Claim
66 words
The method of claim 52 , wherein delaying a first input and delaying the first output clock signals includes propagating the signals through a plurality of delay stages of a coarse delay segment and a plurality of delay stages of a fine delay segment, wherein a delay of each of the fine delay stages is smaller than a delay of each of the coarse delay stages.
Claim 71
Independent Claim
109 words
A method of generating multiple clock signals, the method comprising: delaying a first input clock signal to generate a first output clock signal; delaying the first output clock signal to generate a second output clock signal; delaying a second input clock signal to generate a third output clock signal; delaying the third output clock signal to generate a fourth output clock signal; generating a feedback signal from the fourth output clock signal; and synchronizing the feedback signal and the second input clock signals such that the first, second, third and fourth output clock signals are one-fourth, one-half three-fourths and one clock cycle delayed from the first input clock signal.
Claim 72
Independent Claim
109 words
A method of generating multiple clock signals, the method comprising: delaying a first input clock signal to generate a first output clock signal; delaying the first output clock signal to generate a second output clock signal; delaying a second input clock signal to generate a third output clock signal; delaying the third output clock signal to generate a fourth output clock signal; generating a feedback signal from the fourth output clock signal; and synchronizing the feedback signal and the second input clock signals such that the first, second, third and fourth output clock signals are one-fourth, one-half three-fourths and one clock cycle delayed from the first input clock signal.
Claim 73
Dependent Claim
66 words
The method of claim 54 , wherein delaying a first input and delaying the first output clock signals includes propagating the signals through a plurality of delay stages of a coarse delay segment and a plurality of delay stages of a fine delay segment, wherein a delay of each of the fine delay stages is smaller than a delay of each of the coarse delay stages.
Claim 74
Dependent Claim
64 words
The method of claim 55 , wherein delaying a second input and the third output clock signals includes propagating the signals through a plurality of delay stages of a coarse delay segment and a plurality of delay stages of fine delay segment, wherein a delay of each of the fine delay stages is smaller than a delay of each of the coarse delay stages.
References Cited (Backward Citations)
US5963069A
Cited
US6539072B1
Cited
US6011732A
Cited
US6137325A
Cited
US6289068B1
Cited
US6777995B1
Cited
US6385126B2
Cited
US6445231B1
Cited
US6839860B2
Cited
USPTO Annuity & Maintenance Windows
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