US6904539B2 — Method of determining data transfer speed in data…

Claim 1

Independent Claim 136 words

A method of transferring an encoded data signal including a clock signal and a data signal, comprising the steps of: decoding the encoded data signal to generate a decoded data signal and a write clock signal; storing the decoded data signal in a memory in accordance with the write clock signal; determining a data transfer speed of the encoded data signal using the write clock signal; selecting a read clock signal corresponding to the determined data transfer speed from a plurality of read clock signals, wherein the plurality of read clock signals correspond to a plurality of predetermined data transfer speeds, respectively; reading the decoded data signal stored in the memory in accordance with the read clock signal; and encoding the read decoded data signal and the read clock signal to generate an encoded data signal.

Claim 2

Independent Claim 136 words

A method of transferring an encoded data signal including a clock signal and a data signal, comprising the steps of: decoding the encoded data signal to generate a decoded data signal and a write clock signal; storing the decoded data signal in a memory in accordance with the write clock signal; determining a data transfer speed of the encoded data signal using the write clock signal; selecting a read clock signal corresponding to the determined data transfer speed from a plurality of read clock signals, wherein the plurality of read clock signals correspond to a plurality of predetermined data transfer speeds, respectively; reading the decoded data signal stored in the memory in accordance with the read clock signal; and encoding the read decoded data signal and the read clock signal to generate an encoded data signal.

Claim 3

Dependent Claim 44 words

The method according to claim 1 , wherein the step of determining the data transfer speed includes measuring a time required to store a predetermined number of bits of the encoded data signal in the memory by counting pulses of a reference clock signal.

Claim 4

Dependent Claim 50 words

The method according to claim 1 , wherein the step of determining the data transfer speed includes the steps of: measuring a time required to store a predetermined number of bits of the encoded data signal in the memory; and determining the data transfer speed based on the measured time.

Claim 5

Dependent Claim 27 words

The method of according to claim 3 , wherein the step of measuring a time includes counting pulses of a reference clock signal to measure the time.

Claim 6

Dependent Claim 24 words

The method according to claim 1 , further comprising the step of generating the plurality of read clock signals using a reference clock signal.

Claim 7

Dependent Claim 30 words

The method according to claim 1 , wherein the encoded signal includes a strobe signal and a data signal, which are encoded in accordance with a Data-Strobe Link coding scheme.

Claim 8

Dependent Claim 22 words

The method according to claim 1 , wherein the plurality of data transfer speeds include 100 DMbs, 200 Mbs and 400 Mbs.

Claim 9

Independent Claim 168 words

An apparatus for transferring an encoded data signal including a clock signal and a data signal, comprising: a decoder circuit for decoding the encoded data signal to generate a decoded data signal and write clock signal; a memory, connected to the decoder circuit, for storing the decoded data signal in accordance with the write clock signal; a transfer speed determining circuit for determining a data transfer speed of the encoded data signal in accordance with the write clock signal, wherein the transfer speed determining circuit selects a read clock signal corresponding to the determined data transfer speed from a plurality of read clock signals, wherein the plurality of read clock signals correspond to a plurality of data transfer speeds, respectively, and the decoded data signal is read from the memory in accordance with the read clock signal; and an encoder circuit, connected to the memory and the transfer speed determining circuit, for encoding the decoded data signal and the read clock signal to generate the encoded data signal.

Claim 10

Independent Claim 168 words

An apparatus for transferring an encoded data signal including a clock signal and a data signal, comprising: a decoder circuit for decoding the encoded data signal to generate a decoded data signal and write clock signal; a memory, connected to the decoder circuit, for storing the decoded data signal in accordance with the write clock signal; a transfer speed determining circuit for determining a data transfer speed of the encoded data signal in accordance with the write clock signal, wherein the transfer speed determining circuit selects a read clock signal corresponding to the determined data transfer speed from a plurality of read clock signals, wherein the plurality of read clock signals correspond to a plurality of data transfer speeds, respectively, and the decoded data signal is read from the memory in accordance with the read clock signal; and an encoder circuit, connected to the memory and the transfer speed determining circuit, for encoding the decoded data signal and the read clock signal to generate the encoded data signal.

Claim 11

Dependent Claim 212 words

The apparatus according to claim 8 , wherein the memory includes: a memory cell circuit for storing the decoded data signal; a write pointer, connected td the memory cell circuit, for generating a write address of the memory cell circuit in accordance with the write clock signal; a read pointer, connected to the memory cell circuit, for generating a read address of the memory cell circuit in accordance with the read clock signal; and a pointer comparator, connected to the write pointer and the read pointer, for comparing the write address with the read address to generate a comparison result signal, and wherein the transfer speed determining circuit includes: a timer, connected to the pointer comparator, responsive to the comparison result signal to measure a time required to store a predetermined number of bits of the decoded signal in the memory cell circuit in accordance with the write clock signal; a determining circuit, connected to the timer, for determining the transfer speed based on the time measured by the timer to generate a determination signal; and a clock signal generator circuit, connected to the determining circuit, for selecting a read clock signal corresponding to the determined data transfer speed from the plurality of read clock signals in accordance with the determination signal.

Claim 12

Dependent Claim 25 words

The apparatus according to claim 9 , wherein the clock signal generator circuit generates the plurality of read clock signals using a reference clock signal.

Claim 13

Dependent Claim 49 words

The apparatus according to claim 9 , wherein the timer counts pulses of a reference clock signal in response to the comparison result signal while the predetermined number of bits of the decoded data signal are stored in the memory cell circuit in accordance with the write clock signal.

Claim 14

Dependent Claim 26 words

The method according to claim 8 , further comprising a clock signal generator for generating the plurality of read clock signals using a reference clock signal.

Claim 15

Dependent Claim 22 words

The method according to claim 8 , wherein the plurality of data transfer speeds include 100 Mbs, 200 Mbs and 400 Mbs.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2008-06-06	2008-12-06	2009-06-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2012-06-06	2012-12-06	2013-06-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2016-06-06	2016-12-06	2017-06-07	$7700.00	Window Closed / Lapsed

Method of determining data transfer speed in data transfer apparatus

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