Delay line separator for data bus

Claim 2

A delay line separator for extracting a clock signal from a combined clock/data signal received along a serial data line, said combined clock/data signal including pulses each bounded by a signal level transition of a first type and a signal level transition of a second type, said separator comprising: a one-shot pulse means, connected to said serial data line, for generating a pulse signal having individual pulses corresponding to all transitions of said first type within said data signal; a pulse stretching means for increasing the width of said pulses within said pulse signal; and a delay line means for generating a clock signal from said pulse signal having pulses of increased width, said clock signal being synchronized with said transitions of said first type within said data signal.

Claim 3

The delay line separator of claim 1, wherein said transitions of said first type are rising edge signal level transitions and said transitions of said second type are falling edge signal level transitions.

Claim 4

The delay line separator of claim 1, wherein said transitions of said first type are falling edge signal level transitions and said transitions of said second type are rising edge signal level transitions.

Claim 5

The delay line separator of claim 1, wherein said delay line means includes: a plurality of additional one-shot pulse means, sequentially connected to said pulse stretching means, for successively receiving said pulse signal having pulses of increased width and for generating additional pulses corresponding to said transitions of said first type in said pulse signal, with each of said additional one-shot pulse means including a delay means for delaying said pulse signal by a preselected amount; and OR-gate means, connected to each of said additional one-shot pulse means, for combining output pulses from each of said additional one-shot pulse means to yield the clock signal.

Claim 6

The delay line separator of claim 4, wherein said combined clock/data signal includes a plurality of sequential bit cells with said combined clock/data signal encoded subject to an encoding scheme which ensures at least two transitions of like types within no more than a predefined number N of bit cells and wherein said delay line includes N one-shot pulse means.

Claim 7

The delay line separator of claim 5, wherein said combined signal is encoded with IEEE Standard 4B5B encoding and wherein said delay line includes at least six of said one-shot pulse means.

Claim 8

The delay line separator of claim 4, wherein each of said delay means of said delay line provides a delay of approximately 10 nanoseconds, said pulses of said pulse signal have a width of approximately 10 nanoseconds, and said pulse stretchor increases said pulse width to approximately 20 nanoseconds.

Claim 9

A delay line separator for extracting a clock signal from a combined clock/data signal received along a serial data line, said combined clock/data signal including a plurality of sequential bit cells having a predefined width (W), said data being encoded subject to an encoding scheme which ensures at least two rising-edge transitions within no more than a predefined number (N) of bit cells, said separator comprising: a one-shot pulse means, connected to said serial data line, for generating a pulse signal having an individual pulse corresponding to each rising edge within said data signal; a pulse stretching means for increasing the width of said pulses within said pulse signal to a width approximately equal to said bit cell width W; at least N additional one-shot pulse means, sequentially connected to said pulse stretching means, for successively receiving said pulse signal having pulses of increased width and for generating additional pulses corresponding to rising edges in said pulse signal, with each of said additional one-shot pulse means including a delay means for delaying said pulse signal by amount of time T; and OR-gate means, connected to each of said additional one-shot pulse means, for combining output pulses from each of said additional one-shot pulse means to yield a single clock signal, said clock signal including pulses having a width of W/2.

Claim 10

A delay line separator for extracting a clock signal from a combined clock/data signal received along a serial data line, said combined clock/data signal including a plurality of sequential bit cells having a predefined width (W), said data being encoded subject to an encoding scheme which ensures at least two rising-edge transitions within no more than a predefined number (N) of bit cells, said separator comprising: a one-shot pulse means, connected to said serial data line, for generating a pulse signal having an individual pulse corresponding to each rising edge within said data signal; a pulse stretching means for increasing the width of said pulses within said pulse signal to a width approximately equal to said bit cell width W; at least N additional one-shot pulse means, sequentially connected to said pulse stretching means, for successively receiving said pulse signal having pulses of increased width and for generating additional pulses corresponding to rising edges in said pulse signal, with each of said additional one-shot pulse means including a delay means for delaying said pulse signal by amount of time T; and OR-gate means, connected to each of said additional one-shot pulse means, for combining output pulses from each of said additional one-shot pulse means to yield a single clock signal, said clock signal including pulses having a width of W/2.

Claim 11

The delay line separator of claim 8, wherein said combined clock/data signal is encoded according to 4B5B protocol.

Claim 12

The delay line separator of claim 8, wherein said bit cell width W is 20 nanoseconds.

Claim 13

The delay line separator of claim 8, wherein each of said delay means of said at least N additional one shot means provide a delay of approximately 10 nanoseconds.

Claim 14

The delay line separator of claim 9, wherein N is 6.

Claim 15

The delay line separator of claim 8, wherein each of said one-shot pulse means comprises: a delay means, along a first path, for delaying an output signal from the pulse stretching means by an amount of time T; an inverter means, along a second path, for inverting said output signal from the pulse stretching means; and a NOR-gate means for combining and inverting signals received along said first and second paths, thereby yielding a signal having a single pulse of width T corresponding to each rising edge in said input signal.

Claim 16

The delay line separator of claim 8, wherein said pulse stretching means comprises: a delay means, along a first path, for delaying an output signal from the pulse stretching means by an amount of time T; a second path for transmitting said output signal from said pulse stretching means; and an OR-gate means for combining signals received along said first and second paths, thereby yielding a signal having a single pulse with a pulse-width of approximately twice T.

Claim 17

The delay line separator of claim 8, further including a frequency multiplier circuit connected to a crystal oscillator for receiving a clock signal output from said crystal oscillator, said frequency multiplier including phase-lock loop having, in a continuous loop, a phase detector receiving the clock signal from said crystal oscillator, a loop filter receiving output of the phase detector, and a voltage controlled oscillator receiving an output of the loop filter, and wherein each of said delay means comprises a set of cascaded inverters connected in series to an output of a previous delay means and to an output of said pulse stretching means, with clock inputs of said invertors connected, in parallel, to an output of said loop filter of said phase-lock loop.

Claim 18

The delay line separator of claim 8, further including means for generating delayed clock signals.

Claim 19

The delay line separator of claim 16, wherein said delay elements provide a delayed pulse, delayed by an amount T, along a front output, wherein said delay elements additionally output a signal delayed by T/2 output from a second output of said delay element, and wherein said means for generating delayed clock signals comprises: a second set of one-shot means, each respectively, connected to one of said delay elements of said first set of one shot means, said second set receiving said signals delayed by T/2 from respective second outputs of said delay elements; and a second OR-gate means, connected to each of said additional one-shot pulse means, for combining output pulses from each of said additional one-shot pulse means to yield a second clock signal, said second clock signal including pulses having a width of W/2, said pulses being delayed by T/2 from said clock signal of said first set of one-shot pulse means.

Claim 20

A delay line separator for extracting a clock signal from a combined data/clock signal received along a serial data line, said combined data/clock signal including a plurality of sequential bit cells having a predefined width (W), with selected bit cells being separated by signal level transitions, said signal level transitions being of two types, said data being encoded subject to an encoding scheme which ensures that at least two transitions of like type occur within no more than a predefined number (N) of bit cells, and wherein said combined clock/data signal is influenced by distortion which affects the time between successive transitions of differing types but does not affect the time between successive transitions of like types, said separator comprising: a first one-shot pulse means, connected to said serial data line, for generating a pulse signal having an individual pulse corresponding to each transition of a pre-determined type within said combined clock/data signal; at least N additional one-shot pulse means, sequentially connected to said first one-shot pulse means, for receiving said pulse signal and for generating additional pulses corresponding to each pulse in said pulse signal, with each of said additional one-shot pulse means including a delay means for delaying said pulse signal by an amount equal to said bit cell width W; and OR-gate means, connected to each of said additional one-shot pulse means, for combining output pulses from each of said additional one-shot pulse means to yield a single clock signal, said clock signal including pulses having a width of W/2.

Claim 21

A delay line separator for extracting a clock signal from a combined data/clock signal received along a serial data line, said combined data/clock signal including a plurality of sequential bit cells having a predefined width (W), with selected bit cells being separated by signal level transitions, said signal level transitions being of two types, said data being encoded subject to an encoding scheme which ensures that at least two transitions of like type occur within no more than a predefined number (N) of bit cells, and wherein said combined clock/data signal is influenced by distortion which affects the time between successive transitions of differing types but does not affect the time between successive transitions of like types, said separator comprising: a first one-shot pulse means, connected to said serial data line, for generating a pulse signal having an individual pulse corresponding to each transition of a pre-determined type within said combined clock/data signal; at least N additional one-shot pulse means, sequentially connected to said first one-shot pulse means, for receiving said pulse signal and for generating additional pulses corresponding to each pulse in said pulse signal, with each of said additional one-shot pulse means including a delay means for delaying said pulse signal by an amount equal to said bit cell width W; and OR-gate means, connected to each of said additional one-shot pulse means, for combining output pulses from each of said additional one-shot pulse means to yield a single clock signal, said clock signal including pulses having a width of W/2.

Claim 24

The method of claim 19, wherein said transitions of said first type are rising edge signal level transitions and said transitions of said second type are falling edge signal level transitions.

Claim 25

The method of claim 19, wherein said transitions of said first type are falling edge signal level transitions and said transitions of said second type are rising edge signal level transitions.

Claim 26

The method of claim 19 wherein said step of generating a clock signal includes the steps of: sequentially generating additional pulses corresponding to said transitions of said first type in said pulse signal having pulses of increased width, with each of said additional pulses being successively delayed by a preselected amount; and combining said additional pulses to yield the clock signal.

Claim 27

The method of claim 22, wherein said combined clock/data signal includes a plurality of sequential bit cells with said combined clock/data signal encoded subject to an encoding scheme which ensures at least two transitions of like types within no more than a predefined number N of bit cells and wherein said step of generating additional pulses is applied to generate N additional pulses.

Claim 28

The method of claim 23, wherein said combined signal is encoded with IEEE Standard 4B5B encoding and wherein N is greater than or equal to six.

Claim 29

The method of claim 22, wherein said pulses are delayed by approximately 10 nanoseconds, said pulses of said pulse signal have a width of approximately 10 nanoseconds, and said pulses of said pulse signal are increased to a width of approximately 20 nanoseconds.

Claim 32

The method of claim 26, wherein said input data signal is encoded according to 4B5B protocol.

Claim 33

The method of claim 26, wherein said bit cell width W is 20 nanoseconds.

Claim 34

The method of claim 26, wherein said delay elements of said additional one shot means provide a delay of approximately 10 nanoseconds.

Claim 35

The method of claim 27, wherein N is 6.

Claim 36

The method of claim 26, wherein said step of sequentially generating additional pulses comprises the steps of: delaying said pulse signal having pulses of increased width by an amount of time T to produce a first signal; inverting said pulse signal having pulses of increased width to produce a second signal; and combining and inverting said first and second signals to yield a signal having a single pulse of width T corresponding to each rising edge in said input signal.

Claim 37

The method of claim 26, wherein said step of increasing the width of said pulses in said pulse signal comprises the steps of: delaying said pulse signal having pulses of increased width by an amount of time T to produce a first signal; combining said pulse signal having pulses of increased width and said first signal to yield a signal having a single pulse with a pulse width of approximately twice T.

Claim 38

A delay line separator for extracting a dock signal from a combined clock/data signal received along a serial data line, said combined clock/data signal including pulses bounded by signal level transitions of first and second types, said separator comprising: a one-shot pulse circuit, connected to said serial data line, generating a pulse signal having individual pulses corresponding to all transitions of said first type within said data signal; a pulse stretching circuit, connected to the one-shot pulse circuit, increasing the width of said pulses within said pulse signal; and a delay line circuit, connected to the pulse stretching circuit, generating a clock signal from said pulse signal having pulses of increased width, said clock signal being synchronized with said transitions of said first type within said data signal.

Claim 39

A delay line separator for extracting a dock signal from a combined clock/data signal received along a serial data line, said combined clock/data signal including pulses bounded by signal level transitions of first and second types, said separator comprising: a one-shot pulse circuit, connected to said serial data line, generating a pulse signal having individual pulses corresponding to all transitions of said first type within said data signal; a pulse stretching circuit, connected to the one-shot pulse circuit, increasing the width of said pulses within said pulse signal; and a delay line circuit, connected to the pulse stretching circuit, generating a clock signal from said pulse signal having pulses of increased width, said clock signal being synchronized with said transitions of said first type within said data signal.

Claim 40

The delay line separator of claim 33, wherein said transitions of said first type are rising edge signal level transitions and said transitions of said second type are falling edge signal level transitions.

Claim 41

The delay line separator of claim 33, wherein said transitions of said first type are falling edge signal level transitions and said transitions of said second type are rising edge signal level transitions.

Claim 42

The delay line separator of claim 33, wherein said delay line circuit includes: a plurality of additional one-shot pulse circuits, sequentially connected to said pulse stretching circuit, successively receiving said pulse signal having pulses of increased width and generating additional pulses corresponding to said transitions of said first type in said pulse signal, with each of said additional one-shot pulse circuits including a delay circuit delaying said pulse signal by a preselected amount; and an OR-gate circuit, connected to each of said additional one-shot pulse circuits, combining output pulses from each of said additional one-shot pulse circuits to yield the clock signal.

Claim 43

The delay line separator of claim 36, wherein said combined clock/data signal includes a plurality of sequential bit cells with said combined clock/data signal encoded subject to an encoding scheme which ensures at least two transitions of like types within no more than a predefined number N of bit cells and wherein said delay line includes N one-shot pulse circuits.

Claim 44

The delay line separator of claim 37, wherein said combined signal is encoded with IEEE Standard 4B5B encoding and wherein said delay line includes at least six of said one-shot pulse circuit.

Claim 45

The delay line separator of claim 36, wherein each of said delay circuits of said delay line provides a delay of approximately 10 nanoseconds, said pulses of said pulse signal have a width of approximately 10 nanoseconds, and said pulse stretchor increases said pulse width to approximately 20 nanoseconds.

Claim 46

A delay line separator for extracting a clock signal from a combined clock/data signal received along a serial data line, said combined clock/data signal including a plurality of sequential bit cells having a predefined width (W), said data being encoded subject to an encoding scheme which ensures at least two rising-edge transitions within no more than a predefined number (N) of bit cells, said separator comprising: a one-shot pulse circuit, connected to said serial data line, generating a pulse signal having an individual pulse corresponding to each rising edge within said data signal; a pulse stretching circuit increasing the width of said pulses within said pulse signal to a width approximately equal to said bit cell width W; at least N additional one-shot pulse circuits, sequentially connected to said pulse stretching circuit, successively receiving said pulse signal having pulses of increased width and generating additional pulses corresponding to rising edges in said pulse signal, with each of said additional one-shot pulse circuits including a delay circuit delaying said pulse signal by amount of time T; and an OR-gate circuit, connected to each of said additional one-shot pulse circuits, combining output pulses from each of said additional one-shot pulse circuit to yield a single clock signal, said clock signal including pulses having a width of W/2.

Claim 47

A delay line separator for extracting a clock signal from a combined clock/data signal received along a serial data line, said combined clock/data signal including a plurality of sequential bit cells having a predefined width (W), said data being encoded subject to an encoding scheme which ensures at least two rising-edge transitions within no more than a predefined number (N) of bit cells, said separator comprising: a one-shot pulse circuit, connected to said serial data line, generating a pulse signal having an individual pulse corresponding to each rising edge within said data signal; a pulse stretching circuit increasing the width of said pulses within said pulse signal to a width approximately equal to said bit cell width W; at least N additional one-shot pulse circuits, sequentially connected to said pulse stretching circuit, successively receiving said pulse signal having pulses of increased width and generating additional pulses corresponding to rising edges in said pulse signal, with each of said additional one-shot pulse circuits including a delay circuit delaying said pulse signal by amount of time T; and an OR-gate circuit, connected to each of said additional one-shot pulse circuits, combining output pulses from each of said additional one-shot pulse circuit to yield a single clock signal, said clock signal including pulses having a width of W/2.

Claim 48

The delay line separator of claim 40, wherein said input data signal is encoded according to 4B5B protocol.

Claim 49

The delay line separator of claim 41, wherein N is 6.

Claim 50

The delay line separator of claim 40, wherein said bit cell width W is 20 nanoseconds.

Claim 51

The delay line separator of claim 40, wherein each of said delay circuit of said at least N additional one shot circuit provide a delay of approximately 10 nanoseconds.

Claim 52

The delay line separator of claim 40, wherein each of said one-shot pulse circuits comprises: a delay circuit, along a first path, delaying an output signal from the pulse stretching circuit by an amount of time T; an inverter circuit, along a second path, inverting said output signal from the pulse stretching circuit; and a NOR-gate circuit combining and inverting signals received along said first and second paths, thereby yielding a signal having a single pulse of width T corresponding to each rising edge in said input signal.

Claim 53

The delay line separator of claim 40, wherein said pulse stretching circuit comprises: a delay circuit, along a first path, delaying an output signal from the pulse stretching circuit by an amount of time T; a second path transmitting said output signal from said pulse stretching circuit; and an OR-gate circuit combining signals received along said first and second paths, thereby yielding a signal having a single pulse with a pulse-width of approximately twice T.

Claim 54

The delay line separator of claim 40, further including a frequency multiplier circuit connected to a crystal oscillator receiving a clock signal output from said crystal oscillator, said frequency multiplier including phase-lock loop having, in a continuous loop, a phase detector receiving the clock signal from said crystal oscillator, a loop filter receiving output of the phase detector, and a voltage controlled oscillator receiving an output of the loop filter, and wherein each of said delay circuits comprises a set of cascaded inverters connected in series to an output of a previous delay circuit and to an output of said pulse stretching circuit, with clock inputs of said invertors connected, in parallel, to an output of said loop filter of said phase-lock loop.

Claim 55

The delay line separator of claim 40, further including a circuit generating delayed clock signals.

Claim 56

The delay line separator of claim 48, wherein said delay elements provide a delayed pulse, delayed by an amount T, along a front output, wherein said delay elements additionally output a signal delayed by T/2 output from a second output of said delay element, and wherein said circuit generating delayed clock signals comprises: a second set of one-shot circuits, each respectively, connected to one of said delay elements of said first set of one shot circuits, said second set receiving said signals delayed by T/2 from respective second outputs of said delay elements; and a second OR-gate circuit, connected to each of said additional one-shot pulse circuits, combining output pulses from each of said additional one-shot pulse circuits to yield a second clock signal, said second clock signal including pulses having a width of W/2, said pulses being delayed by T/2 from said clock signal of said first set of one-shot pulse circuits.