Method and apparatus for compensating duty cycle distortion in a data output signal from a memory device by delaying and distorting a reference clock

Claim 3

The method as recited in claim 1 , wherein the reference clock signal comprises falling edges and rising edges, and wherein, when the distorted output clock signal is applied to the data output circuit, the stored data is removed therefrom synchronous with the falling edges and the rising edges of the reference clock signal.

Claim 4

The method as recited in claim 1 , wherein, when the distorted output clock signal is applied to the data output circuit, the data output circuit generates a data output signal comprising the stored data, the data output signal having reduced duty cycle distortion.

Claim 5

The method as recited in claim 3 , wherein the data output signal has a 50% duty cycle.

Claim 6

The method as recited in claim 1 , comprising the act of: determining an amount of data duty cycle distortion introduced by the data output circuit; and wherein the act of distorting the reference clock signal comprises distorting the reference clock signal in phase inverse relationship to the determined amount of duty cycle distortion.

Claim 7

The method as recited in claim 5 , wherein the act of determining the amount of data duty cycle distortion comprises the act of: providing a model of the data output circuit in a feedback path in the synchronization circuit.

Claim 8

The method as recited in claim 6 , wherein the model comprises a copy of the data output circuit.

Claim 9

The method as recited in claim 7 , wherein the data output circuit comprises a latch.

Claim 10

The method as recited in claim 1 , wherein the reference clock signal comprises rising edges and falling edges, and wherein the act of delaying and distorting the reference clock signal comprises the acts of: adjusting timing of the rising edges of the reference clock signal; and adjusting timing of the falling edges of the reference clock signal.

Claim 11

The method as recited in claim 1 , wherein the act of delaying and distorting the reference clock signal comprises: delaying the reference clock signal to generate an output clock signal, wherein the output clock signal comprises rising edges and falling edges; and distorting the output clock signal by adjusting timing of the rising edges of the output clock signal and adjusting timing of the falling edges of the output clock signal to generate the distorted output clock signal.

Claim 12

The method as recited in claim 10 , comprising the acts of: determining an amount of data duty cycle distortion introduced by the data output circuit; and wherein the act of distorting the output clock signal comprises distorting the output clock signal in phase inverse relationship to the determined amount of duty cycle distortion.

Claim 15

The method as recited in claim 12 , comprising the act of adjusting a phase of the reference clock signal to generate the output clock signal having a shifted phase relative to the phase of the reference clock signal.

Claim 16

The method as recited in claim 12 , wherein the reference clock signal comprises falling edges and rising edges, and wherein the acting of distorting the reference duty cycle of the reference clock signal comprises the acts of: adjusting timing of the rising edges; and adjusting timing of the falling edges.

Claim 17

The method as recited in claim 14 , wherein the data output signal comprises falling edges and rising edges, and wherein, when the output clock signal is applied to the output circuit, the falling edges of the data output signal are synchronous with one of the falling edges and the rising edges of the reference clock signal, and the rising edges of the data output signal are synchronous with the other one of the falling edges and the rising edges of the reference clock signal.

Claim 18

The method as recited in claim 14 , wherein the act of adjusting timing of the rising edges is performed separately from the act of adjusting timing of the falling edges.

Claim 19

The method as recited in claim 12 , comprising the act of: determining an amount of data duty cycle distortion introduced by the data output circuit; and wherein the act of distorting the reference duty cycle of the reference clock signal comprises the act of distorting the reference duty cycle in phase inverse relationship to the determined amount of data duty cycle distortion.

Claim 20

The method as recited in claim 17 , wherein the act of determining an amount of data duty cycle distortion comprises the act of: providing a model of the output circuit in a feedback path of the synchronization circuit.

Claim 21

The method as recited in claim 18 , wherein the output circuit comprises a latch.

Claim 22

A processor-based device, comprising: a timing source to provide a reference clock signal; a processor operating synchronous with the reference clock signal; and a synchronous memory device coupled to the processor, the synchronous memory device comprising: a memory array to store data; an output circuit operatively coupled to the memory array to hold data accessed from the memory array in response to a read request from the processor; and a delay lock loop operatively coupled to the timing source and the output circuit, the delay lock loop configured to receive the reference clock signal and to generate an output clock signal based on the reference clock signal, the delay lock loop comprising: a synchronization circuit configured to generate the output clock signal by shifting phase of the reference clock signal and adjusting a clock duty cycle of the reference clock signal, such that, when the output clock signal is applied to the output circuit, a data output signal comprising the data is generated, the data output signal being synchronous with the reference clock signal and having an output duty cycle substantially the same as the clock duty cycle.

Claim 23

A processor-based device, comprising: a timing source to provide a reference clock signal; a processor operating synchronous with the reference clock signal; and a synchronous memory device coupled to the processor, the synchronous memory device comprising: a memory array to store data; an output circuit operatively coupled to the memory array to hold data accessed from the memory array in response to a read request from the processor; and a delay lock loop operatively coupled to the timing source and the output circuit, the delay lock loop configured to receive the reference clock signal and to generate an output clock signal based on the reference clock signal, the delay lock loop comprising: a synchronization circuit configured to generate the output clock signal by shifting phase of the reference clock signal and adjusting a clock duty cycle of the reference clock signal, such that, when the output clock signal is applied to the output circuit, a data output signal comprising the data is generated, the data output signal being synchronous with the reference clock signal and having an output duty cycle substantially the same as the clock duty cycle.

Claim 24

The device as recited in claim 20 , wherein the reference clock signal comprises falling edges and rising edges, and wherein the synchronization circuit comprises a first adjustment circuit configured to adjust timing of the falling edges, and a second adjustment circuit configured to adjust timing of the rising edges.

Claim 25

The device as recited in claim 21 , wherein the synchronization circuit comprises a feedback circuit configured to provide a first feedback signal and a second feedback signal, wherein the first adjustment circuit adjusts the rising edges based on the first feedback signal, and the second adjustment circuit adjusts the falling edges based on the second feedback signal.

Claim 26

The device as recited in claim 22 , wherein the feedback circuit comprises a model of the output circuit.

Claim 27

The device as recited in claim 23 , wherein the output circuit comprises a latch.

Claim 28

The device as recited in claim 23 , wherein the model comprises a copy of the output circuit.

Claim 29

The device as recited in claim 21 , wherein the first adjustment circuit comprises a first delay line and a first phase detector, and wherein the second adjustment circuit comprises a second delay line and a second phase detector.

Claim 30

The device as recited in claim 20 , wherein the output circuit introduces a duty cycle distortion in the output duty cycle of the output data signal, and wherein the synchronization circuit is configured to adjust the clock duty cycle of the reference clock signal in a phase inverse relationship to the duty cycle distortion introduced by the output circuit.

Claim 31

The device as recited in claim 27 , wherein the synchronization circuit comprises a feedback circuit to generate a feedback signal, and the synchronization circuit adjusts the clock duty cycle based on the feedback signal.

Claim 32

The device as recited in claim 28 , wherein the feedback circuit comprises a model of the output circuit.

Claim 33

The device as recited in claim 28 , wherein the feedback circuit comprises a copy of the output circuit.

Claim 34

The device as recited in claim 20 , wherein the synchronous memory device comprises a synchronous dynamic random access memory.

Claim 35

A delay lock loop, comprising: an input configured to receive a reference clock signal having a reference duty cycle; an output configured to couple an output clock signal to an output circuit, the output circuit configured to store data; an adjustment circuit coupled between the input and the output, the adjustment circuit being configured to generate the output clock signal, the output clock signal being phase-shifted relative to the reference clock signal and having an output duty cycle different than the reference duty cycle, wherein, when the output clock signal is applied to the output circuit, the output circuit generates a data output signal comprising the stored data, the data output signal being synchronous with the reference clock signal and having a data output duty cycle substantially the same as the reference duty cycle.

Claim 36

A delay lock loop, comprising: an input configured to receive a reference clock signal having a reference duty cycle; an output configured to couple an output clock signal to an output circuit, the output circuit configured to store data; an adjustment circuit coupled between the input and the output, the adjustment circuit being configured to generate the output clock signal, the output clock signal being phase-shifted relative to the reference clock signal and having an output duty cycle different than the reference duty cycle, wherein, when the output clock signal is applied to the output circuit, the output circuit generates a data output signal comprising the stored data, the data output signal being synchronous with the reference clock signal and having a data output duty cycle substantially the same as the reference duty cycle.

Claim 37

The delay lock loop as recited in claim 32 , wherein the reference clock signal comprises falling edges and rising edges, wherein the output clock signal comprises output falling edges and output rising edges, and wherein the adjustment circuit comprises: a first adjustment circuit to adjust timing of the falling edges of the reference clock signal to generate the output falling edges of the output clock signal; and a second adjustment circuit to adjust timing of the rising edges of the reference clock signal to generate the output rising edges of the output clock signal.

Claim 38

A delay lock loop, comprising: an input configured to receive a reference clock signal having a reference duty cycle; an output configured to couple an output clock signal to an output circuit, the output circuit configured to store data; and an adjustment circuit coupled between the input and the output, the adjustment circuit being configured to adjust the reference duty cycle of the reference clock signal to generate the output clock signal, wherein, when the output clock signal is applied to the output circuit, the output circuit generates a data output signal comprising the stored data, the data output signal being synchronous with the reference clock signal and having reduced duty cycle distortion.

Claim 39

A delay lock loop, comprising: an input configured to receive a reference clock signal having a reference duty cycle; an output configured to couple an output clock signal to an output circuit, the output circuit configured to store data; and an adjustment circuit coupled between the input and the output, the adjustment circuit being configured to adjust the reference duty cycle of the reference clock signal to generate the output clock signal, wherein, when the output clock signal is applied to the output circuit, the output circuit generates a data output signal comprising the stored data, the data output signal being synchronous with the reference clock signal and having reduced duty cycle distortion.

Claim 40

The delay lock loop as recited in claim 34 , wherein the output circuit introduces duty cycle distortion, and wherein the adjustment circuit adjusts the reference duty cycle in phase inverse relationship to the duty cycle distortion introduced by the output circuit.

Claim 41

The delay lock loop as recited in claim 35 , comprising a feedback circuit coupled to the adjustment circuit, the adjustment circuit configured to adjust the reference duty cycle based on the feedback signal, wherein the feedback circuit comprises a model of the output circuit.

Claim 42

The delay lock loop as recited in claim 36 , wherein the model comprises a copy of the output circuit.

Claim 43

The delay lock loop as recited in claim 34 , wherein the reference clock signal comprises rising edges and falling edges, and wherein the adjustment circuit comprises a first adjustment circuit to adjust timing of the rising edges of the reference clock signal, and a second adjustment circuit to adjust timing of the falling edges of the reference clock signal.

Claim 44

An integrated circuit, comprising: a memory array to store data; an input for receiving a reference clock signal; an output circuit to store data accessed from the memory array in response to a read request; and a synchronization circuit coupled to the input and the output circuit, the synchronization circuit configured to generate an output clock signal, such that, when the output clock signal is applied to the output circuit, the output circuit generates an output data signal comprising the data, the output data signal being synchronous with the reference clock signal and having reduced duty cycle distortion.

Claim 45

An integrated circuit, comprising: a memory array to store data; an input for receiving a reference clock signal; an output circuit to store data accessed from the memory array in response to a read request; and a synchronization circuit coupled to the input and the output circuit, the synchronization circuit configured to generate an output clock signal, such that, when the output clock signal is applied to the output circuit, the output circuit generates an output data signal comprising the data, the output data signal being synchronous with the reference clock signal and having reduced duty cycle distortion.

Claim 46

The integrated circuit as recited in claim 39 , wherein the integrated circuit comprises a synchronous memory device.

Claim 47

The integrated circuit as recited in claim 39 , wherein the integrated circuit comprises a synchronous dynamic random access memory.

Claim 50

The method as recited in claim 42 , wherein delaying and distorting the reference clock signal comprises: providing a timing shift in a coarse adjustment circuit to provide a course lock signal; tuning a falling edge of the course lock signal in a first fine adjustment circuit to compensate for distortion in the duty cycle; and tuning a rising edge of the course lock signal in a second fine adjustment circuit to compensate for distortion in the duty cycle.

Claim 51

The method as recited in claim 42 , wherein delaying and distorting the reference clock signal comprises: generating a feedback signal from a feedback circuit coupled to the adjustment circuit; and adjusting the duty cycle of the reference clock signal based on the feedback signal.

Claim 52

The method as recited in claim 44 , wherein generating a feedback signal comprises utilizing a model of the data output circuit to produce the feedback signal.

Claim 53

The method as recited in claim 42 , wherein the modified duty cycle of the distorted output clock signal does not match the duty cycle of the reference clock signal.