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Patent US6882196B2 successfully refreshed from Google Patents.
US6882196B2
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Duty cycle corrector
Assignee: Oracle America Inc
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Filing: 2002-07-18
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Granted: 2005-04-19
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Expires: 2022-07-18
Abstract
Abstract A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.
Inventors
- 👤 Gin Yee
- 👤 Sudhakar Bobba
- 👤 Claude Gauthier
- 👤 Dean Liu
- 👤 Lynn Ooi
- 👤 Pradeep Trivedi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:41
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565; H03K2005/00013; H03K2005/00019; H03K2005/00026; H03K2005/00045
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
100 words
A duty cycle correction device for generating an output clock signal with a desired duty cycle based on an input clock signal, comprising: a pulse generator that inputs the input clock signal and generates a reset signal; a voltage controlled delay element that inputs the reset signal and a bias signal and generates a modified reset signal; a flip-flop configured to generate the output clock signal, wherein the input clock signal and the modified reset signal serve as an inputs to the flip-flop; and a duty cycle controller that inputs the output clock signal and generates the bias signal therefrom.
Claim 2
Dependent Claim
100 words
A duty cycle correction device for generating an output clock signal with a desired duty cycle based on an input clock signal, comprising: a pulse generator that inputs the input clock signal and generates a reset signal; a voltage controlled delay element that inputs the reset signal and a bias signal and generates a modified reset signal; a flip-flop configured to generate the output clock signal, wherein the input clock signal and the modified reset signal serve as an inputs to the flip-flop; and a duty cycle controller that inputs the output clock signal and generates the bias signal therefrom.
Claim 3
Dependent Claim
31 words
The duty cycle correction device of claim 1 , wherein the duty cycle controller monitors a high time of the output clock signal and adjusts the bias signal in response thereto.
Claim 4
Dependent Claim
51 words
The duty cycle correction device of claim 1 , wherein the pulse generator comprises: a delay element that generates an inverted, delayed input clock signal based on the input clock signal; and circuitry that generates the reset signal based on the input clock signal and the inverted, delayed input clock signal.
Claim 5
Dependent Claim
57 words
The duty cycle correction device of claim 1 , wherein the voltage controlled delay element comprises: a first inverter that generates an inverted, delayed reset signal based on the reset signal; circuitry responsive to the bias signal; and a second inverter that generates the modified reset signal based on the inverted, delayed reset signal and the circuitry.
Claim 6
Dependent Claim
62 words
The duty cycle correction device of claim 1 , wherein the voltage controlled delay element further comprises: a plurality of voltage controlled delay elements that generate a plurality of modified reset signals based on the reset signal and the bias signal; and a multiplexer that generates the modified reset signal based on the plurality of modified reset signals and a select signal.
Claim 7
Dependent Claim
34 words
The duty cycle correction device of claim 1 , wherein the flip-flop comprises: an asynchronous resettable flip-flop that generates the output clock signal based on the input clock signal and the modified reset signal.
Claim 8
Independent Claim
113 words
A method for generating an output clock signal with a desired duty cycle based on an input clock signal comprising: inputting the input clock signal to a pulse generator; generating a reset signal from the pulse generator based on the input clock signal; inputting the reset signal and a bias signal to a voltage controlled delay element; generating a modified reset signal from the voltage controlled delay element; generating the output clock signal from a flip-flop, wherein the input clock signal and the modified reset signal serve as an inputs to the flip-flop; inputting the output clock signal to a duty cycle controller; and generating the bias signal from the duty cycle controller.
Claim 9
Independent Claim
113 words
A method for generating an output clock signal with a desired duty cycle based on an input clock signal comprising: inputting the input clock signal to a pulse generator; generating a reset signal from the pulse generator based on the input clock signal; inputting the reset signal and a bias signal to a voltage controlled delay element; generating a modified reset signal from the voltage controlled delay element; generating the output clock signal from a flip-flop, wherein the input clock signal and the modified reset signal serve as an inputs to the flip-flop; inputting the output clock signal to a duty cycle controller; and generating the bias signal from the duty cycle controller.
Claim 10
Dependent Claim
29 words
The method of claim 7 , wherein generating the bias signal comprises: monitoring a high time of the output clock signal and adjusting the bias signal in response thereto.
Claim 11
Dependent Claim
52 words
The method of claim 7 , wherein generating the reset signal using the pulse generator comprises: generating an inverted, delayed input clock signal using a delay element dependent on the input clock signal; and generating the reset signal using circuitry dependent on the input clock signal and the inverted, delayed clock signal.
Claim 12
Dependent Claim
58 words
The method of claim 7 , wherein generating the modified reset signal using the voltage controlled delay element comprises: generating an inverted, delayed reset signal from a first inverter dependent on the reset signal; and generating a modified reset signal from a second inverter dependent on the inverted, delayed reset signal and circuitry dependent on the bias signal.
Claim 13
Dependent Claim
67 words
The method of claim 7 , wherein the generating the modified reset signal comprises: inputting the reset signal and the bias signal to a plurality of voltage controlled delay elements; generating a plurality of modified reset signals using the plurality of voltage controlled delay elements; inputting the plurality of modified reset signals and select signals to a multiplexer; and generating the modified reset signal using the multiplexer.
Claim 14
Dependent Claim
41 words
The method of claim 7 , wherein the generating the output clock signal using the flip-flop comprises: inputting the input clock signal and the modified reset signal to a resettable flip-flop; and generating the output clock signal from the resettable flip-flop.
Claim 15
Independent Claim
100 words
An apparatus for generating an output clock signal with a desired duty cycle dependent on an input clock signal, comprising: means for generating a reset signal based on the input clock signal; means for generating a modified reset signal based on the reset signal and a bias signal, wherein a delay of the means for generating is controlled by the bias signal; a flip-flop for generating the output clock signal, wherein the input clock signal and the modified reset signal serve as an inputs to the flip-flop; and means for generating the bias signal based on the output clock signal.
Claim 16
Independent Claim
100 words
An apparatus for generating an output clock signal with a desired duty cycle dependent on an input clock signal, comprising: means for generating a reset signal based on the input clock signal; means for generating a modified reset signal based on the reset signal and a bias signal, wherein a delay of the means for generating is controlled by the bias signal; a flip-flop for generating the output clock signal, wherein the input clock signal and the modified reset signal serve as an inputs to the flip-flop; and means for generating the bias signal based on the output clock signal.
Claim 17
Independent Claim
162 words
An apparatus for generating an output clock signal with a desired duty cycle dependent on an input clock signal, comprising: a pulse generator having an input operatively connected to the input clock signal, wherein the pulse generator outputs a reset signal in response thereto; a voltage controlled delay element having an input operatively connected to an output of the pulse generator, wherein the voltage controlled delay element outputs a modified reset signal in response to a bias signal and the reset signal; a flip-flop having an input operatively connected to the input clock signal, wherein the flip-flop outputs the output clock signal in response to the modified reset signal and the input clock signal, wherein the modified reset signal and the input clock signal serve as inputs to the flip-flop; and a duty cycle controller having an input operatively connected to an output of the flip-flop, wherein the duty cycle controller outputs the bias signal in response to the output clock signal.
Claim 18
Independent Claim
162 words
An apparatus for generating an output clock signal with a desired duty cycle dependent on an input clock signal, comprising: a pulse generator having an input operatively connected to the input clock signal, wherein the pulse generator outputs a reset signal in response thereto; a voltage controlled delay element having an input operatively connected to an output of the pulse generator, wherein the voltage controlled delay element outputs a modified reset signal in response to a bias signal and the reset signal; a flip-flop having an input operatively connected to the input clock signal, wherein the flip-flop outputs the output clock signal in response to the modified reset signal and the input clock signal, wherein the modified reset signal and the input clock signal serve as inputs to the flip-flop; and a duty cycle controller having an input operatively connected to an output of the flip-flop, wherein the duty cycle controller outputs the bias signal in response to the output clock signal.
Claim 19
Dependent Claim
20 words
The apparatus of claim 14 , wherein the output of the duty cycle controller is operatively connected to a capacitance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-04-18 | 2008-10-18 | 2009-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-04-18 | 2012-10-18 | 2013-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-04-18 | 2016-10-18 | 2017-04-19 | $7700.00 | Window Closed / Lapsed |