Waveform shaping device and clock supply apparatus

Claim 2

A waveform shaping device which converts a waveform of an input clock to output an output clock, comprising: a first variable delay circuit which receives said input clock, delays said input clock by a first delay quantity that is changed monotonously with a control signal, and outputs a first delay clock, wherein an upper bound of said first delay quantity is set to be more than one cycle and less than two cycles of said input clock; a second variable delay circuit which at an input side receives one of said input clock and said first delay clock to be delayed according to said control signal by a second delay quantity which is changed with a constant ratio that is less than 1 with respect to said first delay quantity, and outputs a second delay clock at an output side thereof; a control portion which compares phases of said input clock and said first delay clock, and generates said control signal according to a result of the comparison; and an SR flip-flop which has a set terminal and a reset terminal connected to said input and output sides of said second variable delay circuit respectively, and outputs an output signal as said output clock; wherein said control portion changes said control signal in such a manner so that said first delay quantity is decreased when the phase of said first delay clock is later than a phase of said input clock, and so that said first delay quantity is increased when said phase of said first delay clock is earlier than the phase of said input clock.

Claim 3

The waveform shaping device as defined in claim 1, wherein said control portion includes: a phase comparator which compares the phases of said input clock and said first delay clock, selects either of an up signal and a down signal according to whether one of said input clock and said first delay clock is later or earlier than the other clock, and outputs a selected signal over a period which is equivalent to a phase difference for each cycle of said input clock; a charging pump circuit for selectively outputting one or the other of positive and negative currents over a period in which said up signal or said down signal is outputted respectively; and a loop filter which has a capacity element, stores said positive and negative currents outputted from said charging pump in said capacity element, and outputs the voltage of said capacity element as said control signal.

Claim 4

The waveform shaping device as defined in claim 1, wherein said first variable delay circuit and said second variable delay circuit have respectively a first part and a second part of a group of unit delay elements having the same structure that are cascade-connected so as to be arranged straight; each of said unit delay elements forming said group includes an inverter for sending a signal in a delay time which is reduced as a supplied source current is increased, and a current source for supplying said source current to said inverter in response to a bias signal; and said first variable delay circuit and said second variable delay circuit further share a single bias circuit portion for supplying, in response to said control signal, a common signal as said bias signal to each said current source respectively belonging to each of said unit delay elements forming said group.

Claim 5

The waveform shaping device as defined in claim 1, wherein said first variable delay circuit includes: a first fixed delay circuit which has a group of first unit delay elements that are cascade-connected, and outputs, as a first signal string, a string of output signals fetched every first constant number of said first unit delay elements; and a first selector which is connected to said first fixed delay circuit, selects a signal from said first signal string in response to a selection signal of a digital form expressing a binary number in such a manner that a delay quantity varies monotonously with said binary number, and outputs a selected signal as said first delay clock; wherein said second variable delay circuit includes: a second fixed delay circuit which has a group of second unit delay elements that are cascade-connected, and outputs, as a second signal string, a string of output signals fetched every second constant number of said second unit delay elements; and a second selector which is connected to said second fixed delay circuit, selects, from said second signal string in response to said selection signal, a signal which has a delay quantity having said constant ratio to a delay quantity of said signal selected by said first variable delay circuit, and outputs a selected signal as said second delay clock; and wherein said control portion sends said selection signal as said control signal.

Claim 6

The waveform shaping device as defined in claim 4, wherein said first and second selectors have the same structure, and a connecting relationship between said first selector and said first fixed delay circuit is set identical to a connecting relationship between said second selector and said second fixed delay circuit, said first and second unit delay elements have the same structure, and said first constant number is set greater than said second constant number.

Claim 7

The waveform shaping device as defined in claim 4, wherein said first and second selectors have the same structure, said first and second fixed delay circuits have the same structure, said control portion sends said selection signal corresponding to a binary number as a parallel signal, a connecting relationship between said first selector and said first fixed delay circuit is set identical to a connecting relationship between said second selector and said second fixed delay circuit, and a wiring between said first or second selector and said control portion is connected in such a manner that said control signal is bit-shifted.

Claim 8

The waveform shaping device as defined in claim 4, wherein said control portion includes: a D latch that has a data input terminal and a clock input terminal to which one and the other of said first delay clock and said input clock are inputted respectively, and updates an output according to a level of a signal of said data input terminal every leading edge, to an active level, of a signal of said clock input terminal; a first counter for selectively executing count-up and count-down in the cycle of said input clock according to the level of said output of said D latch, and a second counter for increasing and decreasing a count value synchronously with said input clock every time said first counter overflows and underflows respectively, and for sending said count value as said selection signal.

Claim 9

The waveform shaping device as defined in claim 1, further comprising: N (≧1) third variable delay circuits which are sequentially cascade-connected after said second variable delay circuit and have the same structure as that of said second variable delay circuit, and to which said control signal is inputted as a signal for controlling a delay quantity, and said device, referring to said SR flip-flop as a first SR flip-flop, further comprising, M second SR flip-flops having set and reset terminals connected to M (1≦M≦N) input and output sides of said N third variable delay circuits respectively.

Claim 10

The waveform shaping device as defined in claim 8, wherein said N is an even number and said M is N/2, said first SR flip-flop and said M second SR flip-flops are connected every other circuit of a group of variable delay circuits which are formed by said second variable delay circuit and said N third variable delay circuits and are cascade-connected, and said constant ratio is set to 1/(N+2), said waveform shaping device further comprising an OR circuit for calculating and outputting a logical OR of the output signals of said first SR flip-flop and said M second SR flip-flops.

Claim 11

The waveform shaping device as defined in claim 1, further comprising an offset generating portion which is inserted between said control portion and said second variable delay circuit, and superposes an offset signal on said control signal sent from said control portion to send a superposed signal to said second variable delay circuit.

Claim 12

The waveform shaping device as defined in claim 1, wherein said SR flip-flop includes two one-shot pulse circuits for generating a one-shot pulse synchronously with the leading edge, to an active level, of clocks inputted to said set terminal and said reset terminal respectively.

Claim 13

The waveform shaping device as defined in claim 1, further comprising a one-shot pulse circuit for outputting a one-shot pulse synchronously with the leading edge, to an active level, of said input clock inputted from the outside, wherein said one shot-pulse is supplied to each portion of said waveform shaping device except for said one-shot pulse circuit in place of said input clock.

Claim 14

A waveform shaping device which converts a waveform of an input clock to output an output clock, comprising: a one-shot pulse circuit for outputting a one-shot pulse synchronously with a leading edge of said input clock to an active level; a first variable delay circuit which receives said one-shot pulse, delays said one-shot pulse by a first delay quantity that is changed monotonously with a control signal, and outputs a delay clock, wherein an upper bound of said first delay quantity is set to be more than one cycle and less than two cycles of said input clock; a second variable delay circuit which at an input side receives one of said one-shot pulse and said delay clock, and outputs a delay signal string which is sequentially delayed with a delay width that is changed according to said control signal in such a manner that a second delay quantity of a signal on a last portion keeps a constant ratio which is less than 1 with respect to said first delay quantity; a control portion which compares phases of said one-shot pulse and said delay clock, and generates said control signal according to a result of the comparison; and an OR circuit which calculates a logical OR of said delay clock received by said second variable delay circuit and said delay signal string, and outputs said logical OR as said output clock; wherein said control portion changes said control signal in such a manner so that said first delay quantity is decreased when said phase of said delay clock is later than the phase of said one-shot pulse, and so that said first delay quantity is increased when said phase of said delay clock is earlier than the phase of said one-shot pulse.

Claim 15

A waveform shaping device which converts a waveform of an input clock to output an output clock, comprising: a one-shot pulse circuit for outputting a one-shot pulse synchronously with a leading edge of said input clock to an active level; a first variable delay circuit which receives said one-shot pulse, delays said one-shot pulse by a first delay quantity that is changed monotonously with a control signal, and outputs a delay clock, wherein an upper bound of said first delay quantity is set to be more than one cycle and less than two cycles of said input clock; a second variable delay circuit which at an input side receives one of said one-shot pulse and said delay clock, and outputs a delay signal string which is sequentially delayed with a delay width that is changed according to said control signal in such a manner that a second delay quantity of a signal on a last portion keeps a constant ratio which is less than 1 with respect to said first delay quantity; a control portion which compares phases of said one-shot pulse and said delay clock, and generates said control signal according to a result of the comparison; and an OR circuit which calculates a logical OR of said delay clock received by said second variable delay circuit and said delay signal string, and outputs said logical OR as said output clock; wherein said control portion changes said control signal in such a manner so that said first delay quantity is decreased when said phase of said delay clock is later than the phase of said one-shot pulse, and so that said first delay quantity is increased when said phase of said delay clock is earlier than the phase of said one-shot pulse.

Claim 16

A waveform shaping device which converts a waveform of an input clock to output an output clock, comprising: a variable delay circuit which receives said input clock, delays said input clock by a delay quantity that is changed monotonously with a control signal, and outputs a delay clock, wherein an upper bound of said delay quantity is set to be less than one cycle of said input clock; an SR flip-flop that has a set terminal and a reset terminal which respectively receive said input clock and said delay clock, and outputs an output signal as said output clock; an integrator for integrating said output clock and outputting an integrated clock; and a differential amplifier which receives the integrated clock output from said integrator at a first input and a reference signal at a second input, amplifies a difference in value between said first and second inputs so as to decrease said delay quantity when a value of one of said first and second inputs is greater than a value of another of said first and second inputs and to increase said delay quantity when said value of said one of said first and second inputs is smaller than said value of said another of said first and second inputs, and outputs an amplified signal as said control signal.

Claim 17

A waveform shaping device which converts a waveform of an input clock to output an output clock, comprising: a variable delay circuit which receives said input clock, delays said input clock by a delay quantity that is changed monotonously with a control signal, and outputs a delay clock, wherein an upper bound of said delay quantity is set to be less than one cycle of said input clock; an SR flip-flop that has a set terminal and a reset terminal which respectively receive said input clock and said delay clock, and outputs an output signal as said output clock; an integrator for integrating said output clock and outputting an integrated clock; and a differential amplifier which receives the integrated clock output from said integrator at a first input and a reference signal at a second input, amplifies a difference in value between said first and second inputs so as to decrease said delay quantity when a value of one of said first and second inputs is greater than a value of another of said first and second inputs and to increase said delay quantity when said value of said one of said first and second inputs is smaller than said value of said another of said first and second inputs, and outputs an amplified signal as said control signal.

Claim 18

The waveform shaping device as defined in claim 14, further comprising a reference signal generating portion for generating said reference signal, wherein said reference signal has a constant value.

Claim 19

A waveform shaping device which converts a waveform of an input clock to output an output clock, comprising: a fixed delay circuit which has a group of unit delay elements that are cascade-connected, and outputs a signal string that is obtained by sequentially delaying said input clock every constant number of said unit delay elements; and a selector which, is connected to said fixed delay circuit, selects a signal from said signal string in response to a selection signal of a digital form expressing a binary number in such a manner that a delay quantity has a monotonous relationship with said binary number, and outputs a selected signal as a delay clock; an SR flip-flop that has a set terminal and a reset terminal which respectively receive said input clock and said delay clock, and outputs an output signal as said output clock; a first counter for selectively executing count-up and count-down in a smaller cycle than said input clock according to a level of said output clock; and a second counter for selectively increasing and decreasing a count value in such a manner that a deviation of the duty ratio of said output clock from 50% is eliminated every time said first counter overflows and underflows, and for sending said count value as said selection signal.

Claim 20

A waveform shaping device which converts a waveform of an input clock to output an output clock, comprising: a fixed delay circuit which has a group of unit delay elements that are cascade-connected, and outputs a signal string that is obtained by sequentially delaying said input clock every constant number of said unit delay elements; and a selector which, is connected to said fixed delay circuit, selects a signal from said signal string in response to a selection signal of a digital form expressing a binary number in such a manner that a delay quantity has a monotonous relationship with said binary number, and outputs a selected signal as a delay clock; an SR flip-flop that has a set terminal and a reset terminal which respectively receive said input clock and said delay clock, and outputs an output signal as said output clock; a first counter for selectively executing count-up and count-down in a smaller cycle than said input clock according to a level of said output clock; and a second counter for selectively increasing and decreasing a count value in such a manner that a deviation of the duty ratio of said output clock from 50% is eliminated every time said first counter overflows and underflows, and for sending said count value as said selection signal.

Claim 21

A waveform shaping device which converts a waveform of an input clock to output an output clock, comprising: a first variable delay circuit which receives said input clock, delays said input clock by a first delay quantity that is changed monotonously with a control signal and outputs a first delay clock, wherein an upper bound of said first delay quantity is set to be more than one cycle and less than two cycles of said input clock; a second variable delay circuit which at an input side receives one of said input clock and said first delay clock to be delayed according to said control signal by a second delay quantity which is changed with a constant ratio of 1/4 with respect to said first delay quantity, and outputs a second delay clock at an output side; a control portion which compares phases of said input clock and said first delay clock, and generates said control signal according to a result of the comparison; and an exclusive OR circuit which calculates exclusive-OR of signals on the input and output sides of said second variable delay circuit, and outputs said exclusive-OR as said output clock; wherein said control portion changes said control signal in such a manner that said first delay quantity is decreased when said phase of said first delay clock is later than said phase of said input clock, and that said first delay quantity is increased when said phase of said first delay clock is earlier than said phase of said input clock.

Claim 22

A waveform shaping device which converts a waveform of an input clock to output an output clock, comprising: a first variable delay circuit which receives said input clock, delays said input clock by a first delay quantity that is changed monotonously with a control signal and outputs a first delay clock, wherein an upper bound of said first delay quantity is set to be more than one cycle and less than two cycles of said input clock; a second variable delay circuit which at an input side receives one of said input clock and said first delay clock to be delayed according to said control signal by a second delay quantity which is changed with a constant ratio of 1/4 with respect to said first delay quantity, and outputs a second delay clock at an output side; a control portion which compares phases of said input clock and said first delay clock, and generates said control signal according to a result of the comparison; and an exclusive OR circuit which calculates exclusive-OR of signals on the input and output sides of said second variable delay circuit, and outputs said exclusive-OR as said output clock; wherein said control portion changes said control signal in such a manner that said first delay quantity is decreased when said phase of said first delay clock is later than said phase of said input clock, and that said first delay quantity is increased when said phase of said first delay clock is earlier than said phase of said input clock.