Patent US6862202B2 successfully refreshed from Google Patents.
US6862202B2
Expired / Lapsed
US
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Low power memory module using restricted device activation
Assignee: Round Rock Research LLC
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Filing: 2003-09-23
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Granted: 2005-03-01
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Expires: 2023-09-23
Abstract
Abstract A memory module for an electronic device provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.
Inventors
- 👤 Scott Schaefer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:37
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
83 words
A method of operating an electronic device having a plurality of memory dice, each memory die having at least two sub-arrays therein, the method comprising: individually addressing each sub-array of each said memory die by communicating an address to that sub-array across an address bus coupled to all said memory dice, and by individually selecting said individual memory die from among said plurality of memory dice, while the remainder of said memory dice except said individual memory die remain in a standby mode.
Claim 2
Independent Claim
83 words
A method of operating an electronic device having a plurality of memory dice, each memory die having at least two sub-arrays therein, the method comprising: individually addressing each sub-array of each said memory die by communicating an address to that sub-array across an address bus coupled to all said memory dice, and by individually selecting said individual memory die from among said plurality of memory dice, while the remainder of said memory dice except said individual memory die remain in a standby mode.
Claim 3
Dependent Claim
21 words
The method of claim 1 , wherein said plurality of memory dice are formed as a part of a memory module.
Claim 4
Dependent Claim
13 words
The method of claim 1 , wherein said electronic device comprises a computer.
Claim 5
Independent Claim
76 words
A method of operating an electronic device having a plurality of memory dice associated therewith, each memory die having at least two sub-arrays therein, the method comprising: addressing every sub-array of said selected memory die by communicating an address specific to a memory cell of each sub-array across an address bus coupled to each memory die of said plurality of memory dice; and accessing one memory cell in every sub-array of only said selected memory die.
Claim 6
Independent Claim
76 words
A method of operating an electronic device having a plurality of memory dice associated therewith, each memory die having at least two sub-arrays therein, the method comprising: addressing every sub-array of said selected memory die by communicating an address specific to a memory cell of each sub-array across an address bus coupled to each memory die of said plurality of memory dice; and accessing one memory cell in every sub-array of only said selected memory die.
Claim 7
Dependent Claim
32 words
The method of claim 4 , further comprising maintaining at least one memory die of said plurality of dice in a standby mode, while accessing said memory cell in said selected sub-array.
Claim 8
Dependent Claim
34 words
The method of claim 4 , wherein said individual selection of said at least one individual memory die comprises decoding a plurality of activation signals to determine the memory die to be individually selected.
Claim 9
Dependent Claim
45 words
The method of claim 4 , further comprising: addressing a number of said memory dice from said plurality of memory dice; and enabling only one die from said plurality of memory dice to access a number of data bits from only said selected memory die.
Claim 10
Independent Claim
142 words
A method of configuring an electronic system having a plurality of memory devices therein, comprising: providing a plurality of memory dice, each memory die having a plurality of sub-arrays therein; coupling a plurality of data lines to each memory die, with each data line coupled to only one sub-array in each memory die; coupling an address bus to each memory die, said address bus configured to allow access of one memory cell in each sub-array of said plurality of sub-arrays in each die of said plurality of dice; and providing at least one chip select mechanism to facilitate individual selection of each memory die, said system configured to allow fewer than all of said plurality of memory dice to be selected and activated, while the remaining memory dice of said plurality of memory dice are unselected and in a low power mode.
Claim 11
Independent Claim
142 words
A method of configuring an electronic system having a plurality of memory devices therein, comprising: providing a plurality of memory dice, each memory die having a plurality of sub-arrays therein; coupling a plurality of data lines to each memory die, with each data line coupled to only one sub-array in each memory die; coupling an address bus to each memory die, said address bus configured to allow access of one memory cell in each sub-array of said plurality of sub-arrays in each die of said plurality of dice; and providing at least one chip select mechanism to facilitate individual selection of each memory die, said system configured to allow fewer than all of said plurality of memory dice to be selected and activated, while the remaining memory dice of said plurality of memory dice are unselected and in a low power mode.
Claim 12
Dependent Claim
16 words
The method of claim 8 wherein said memory dice are physically coupled to a memory module.
Claim 13
Dependent Claim
12 words
The method of claim 8 wherein said electronic system comprises a computer.
Claim 14
Dependent Claim
20 words
The method of claim 1 further comprising providing a memory die having only one sub-array which supplies a parity bit.
Claim 15
Dependent Claim
20 words
The method of claim 4 further comprising providing a memory die having only one sub-array which supplies a parity bit.
Claim 16
Dependent Claim
20 words
The method of claim 8 further comprising providing a memory die having only one sub-array which supplies a parity bit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-02-29 | 2008-08-30 | 2009-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-02-29 | 2012-08-30 | 2013-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-02-29 | 2016-08-30 | 2017-03-01 | $7700.00 | Window Closed / Lapsed |