Patent US6803885B1 successfully refreshed from Google Patents.
US6803885B1
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Method and system for displaying information using a transportable display chip
Assignee: Silicon Display Inc
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Filing: 1999-06-21
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Granted: 2004-10-12
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Expires: 2019-06-21
Abstract
Abstract A system for displaying information using a display chip ( 1 ) is disclosed. The display system comprises a controller array ( 24 ) operable to send image data to a display array ( 30 ). The display array ( 30 ) has a plurality of pixels ( 96 ) with each pixel ( 96 ) having at least two memory storage bits per pixel ( 92, 94 ).
Inventors
- 👤 Karl M. Guttag
- 👤 Gerald D. Rogers
- 👤 Ronnie N. Dunn
- 👤 Patrick R. Antaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:43
CPC Classifications
G; G02; G02B; G02B27/00; G02B27/01; G02B27/017; G02B27/0172; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3648; G02B2027/0178; G02B5/00; G02B5/30; G09G2300/00; G09G2300/08; G09G2300/0809; G09G2300/0842; G09G2310/00; G09G2310/02; G09G2310/0235; G09G3/2007; G09G3/2018; G09G3/2022; G09G3/3614
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
191 words
A display device comprising: a controller chip comprising: a memory data array on the controller chip operable to store data values associated with an image to be displayed; and a controller on the controller chip operable to control transmission of the data values stored in the memory data array out of the memory data array and off the control chip; a display chip operable to receive the transmitted data values from the control chip and display the image, comprising: a display array comprising a plurality of pixels; a display chip memory operable to store at least two bits of data per pixel; and a logic arrangement within the display chip operable to retrieve values from the display chip memory, perform logical or arithmetic operations on the data values, and selectively transmit results back to the display chip memory; a data bus operable to carry the transmission of data values stored in the memory data array to the display chip; and wherein the logic arrangement on the display chip is operable to retrieve and transmit data values from and to the display chip memory over a link other than the data bus.
Claim 2
Dependent Claim
191 words
A display device comprising: a controller chip comprising: a memory data array on the controller chip operable to store data values associated with an image to be displayed; and a controller on the controller chip operable to control transmission of the data values stored in the memory data array out of the memory data array and off the control chip; a display chip operable to receive the transmitted data values from the control chip and display the image, comprising: a display array comprising a plurality of pixels; a display chip memory operable to store at least two bits of data per pixel; and a logic arrangement within the display chip operable to retrieve values from the display chip memory, perform logical or arithmetic operations on the data values, and selectively transmit results back to the display chip memory; a data bus operable to carry the transmission of data values stored in the memory data array to the display chip; and wherein the logic arrangement on the display chip is operable to retrieve and transmit data values from and to the display chip memory over a link other than the data bus.
Claim 3
Dependent Claim
28 words
The system of claim 1 , wherein a portion of the display chip memory is organized to fit substantially under the plurality of pixels of the pixel arrangement.
Claim 4
Dependent Claim
21 words
The system of claim 1 , wherein a portion of the display chip memory bits is not under the display array.
Claim 5
Dependent Claim
30 words
The system of claim 1 , wherein a portion of the display chip memory is operable to control at least one of the plurality of pixels on or off state.
Claim 6
Dependent Claim
20 words
The system of claim 1 , wherein there are an integer number of storage bits physically associated with each pixel.
Claim 7
Dependent Claim
31 words
The system of claim 1 , wherein multiple bits of memory may be placed under multiple pixels and wherein the ratio of bits per pixel may not be an integer number.
Claim 8
Dependent Claim
23 words
The system of claim 1 , wherein the display chip memory comprises a shift register operable to store multiple memory bits per pixel.
Claim 9
Dependent Claim
16 words
The system of claim 1 , wherein the display array is a liquid crystal display chip.
Claim 10
Dependent Claim
19 words
The system of claim 1 , wherein the display array is mounted in a frame intended for headset use.
Claim 11
Dependent Claim
17 words
The system of claim 9 , wherein the frame further comprises an earpiece mounted on the frame.
Claim 12
Dependent Claim
17 words
The system of claim 9 , wherein the frame further comprises a microphone mounted on the frame.
Claim 13
Dependent Claim
22 words
The system of claim 1 , wherein the arithmetic or logical operation is performed by logic directly associated with a given pixel.
Claim 14
Dependent Claim
50 words
The system of claim 1 , wherein the arithmetic or logical operation involves selectively sending data values from one or more memory storage bits in the display chip memory to processing logic which can selectively send results to the same or other memory storage bits within the display chip memory.
Claim 15
Dependent Claim
33 words
The system of claim 1 , wherein the logic arrangement can manipulate a portion of the display chip memory that control the pixels as a sequence of steps executed over multiple clock cycles.
Claim 16
Dependent Claim
14 words
The system of claim 1 , wherein the logical operation is a DC restore.
Claim 17
Dependent Claim
22 words
The system of claim 1 , wherein the logic arrangement comprises a separate logic circuit on the display chip for each pixel.
Claim 18
Independent Claim
108 words
A system for displaying information on a display comprising: a data router operable to receive and send display data; and a display chip comprising a n-column by m-row pixel arrangement, having at least two bits of storage memory within the display chip for every pixel in the display, the display operable to receive display data from the data router, the display further comprising a logic arrangement within the display chip operable to retrieve data values from one or more of the bits of storage memory, perform logical or arithmetic operations on the data values, and selectively transmit results to one or more of the bits of storage memory.
Claim 19
Independent Claim
108 words
A system for displaying information on a display comprising: a data router operable to receive and send display data; and a display chip comprising a n-column by m-row pixel arrangement, having at least two bits of storage memory within the display chip for every pixel in the display, the display operable to receive display data from the data router, the display further comprising a logic arrangement within the display chip operable to retrieve data values from one or more of the bits of storage memory, perform logical or arithmetic operations on the data values, and selectively transmit results to one or more of the bits of storage memory.
Claim 20
Dependent Claim
32 words
The system of claim 17 , further comprising a shift register operable to receive display data from the data router and present display data to the display one row at a time.
Claim 21
Dependent Claim
29 words
The system of claim 17 , wherein the display is divided into an upper half and a lower half and there is a separate shift register for each half.
Claim 22
Dependent Claim
55 words
The system of claim 17 , wherein there are two or more memory bits associated with each pixel and wherein the first bit is a display memory bit operable to store a bit value to be displayed and the second bit is a load bit memory operable to store one or more bits of data.
Claim 23
Dependent Claim
19 words
The system of claim 20 , wherein the load bit will control the same pixel as the display bit.
Claim 24
Dependent Claim
21 words
The system of claim 20 , wherein data stored in the load bit memory passes directly to the display bit memory.
Claim 25
Dependent Claim
23 words
The system of claim 20 , wherein the data stored in the pixel memory controls the pixel the pixel memory is coupled to.
Claim 26
Dependent Claim
32 words
The system of claim 23 , wherein the cell further comprises a logic circuit coupled to the pixel and operable to invert and display the last data value displayed by the pixel.
Claim 27
Dependent Claim
27 words
The system of claim 17 , wherein the data stored in at least some of the memory bits are manipulated logically or arithmetically before controlling a pixel.
Claim 28
Dependent Claim
25 words
The system of claim 17 , wherein the logic operation is an inversion of the data and the inverted data is redisplayed at the pixel.
Claim 29
Dependent Claim
30 words
The system of claim 17 , further comprising at least one shared logic block operable to perform logic and arithmetic functions on the bit values stored in the pixel memory.
Claim 30
Dependent Claim
22 words
The system of claim 17 , wherein the logic arrangement comprises a separate logic circuit on the display chip for each pixel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-10-12 | 2008-04-12 | 2008-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-10-12 | 2012-04-12 | 2012-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-10-12 | 2016-04-12 | 2016-10-12 | $7700.00 | Window Closed / Lapsed |