US5210705A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital filtering with single-instruction, multiple-data processor
Assignee: Texas Instruments Inc
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Filing: 1992-05-20
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Granted: 1993-05-11
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Expires: 2012-05-20
Abstract
Abstract A single-instruction multiple-data processor (10) has an input layer especially designed for high data input and output rates. The processor (10) has a number of processing elements (20), each corresponding to incoming data samples. The processing elements (20) are interleaved so that a set of samples can be input in parallel. The processor (10) is programmable, which makes it especially useful for digital filtering. Near-neighbor communications (41) among processing elements (20) realize the delays required for horizontal filtering.
Inventors
- 👤 Gerard Chauvel
- 👤 Hiroshi Miyaguchi
- 👤 Jimmie D. Childers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:20
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/20; H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H04; H04N; H04N7/00; H04N7/01; H04N7/0117; H04N7/012; H04N7/0127; H04N7/0132; H04N5/00; H04N5/14; Y; Y10; Y10S; Y10S348/00; Y10S348/914
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
118 words
A digital processing system for implementing a horizontal digital filter, comprising: a single-instruction multiple-data processor having a number of processing elements for receiving data samples in an ordered sequence, and having an arithmetic unit associated with each processing element of performing computations, and having next-neighbor communications between said processing elements, wherein said processor is programmed to perform computations to implement said filter by using said processing elements as taps of said filter, such that said data samples are output from said processing elements in said ordered sequence; a processor control unit for providing timing and control signals to said processor; and an instruction generator for providing instructions to said processor said instructions including instructions for performing said computations.
Claim 2
Dependent Claim
118 words
A digital processing system for implementing a horizontal digital filter, comprising: a single-instruction multiple-data processor having a number of processing elements for receiving data samples in an ordered sequence, and having an arithmetic unit associated with each processing element of performing computations, and having next-neighbor communications between said processing elements, wherein said processor is programmed to perform computations to implement said filter by using said processing elements as taps of said filter, such that said data samples are output from said processing elements in said ordered sequence; a processor control unit for providing timing and control signals to said processor; and an instruction generator for providing instructions to said processor said instructions including instructions for performing said computations.
Claim 3
Dependent Claim
24 words
The digital processing system of claim 1 and further comprising an interface for downloading said instructions from a host development system to said processor.
Claim 4
Dependent Claim
23 words
The digital processing system of claim 1, wherein each of said processing elements is associated with an element of a data input register.
Claim 5
Dependent Claim
19 words
The digital processing system of claim 1, wherein each of said processing elements is associated with a local memory.
Claim 6
Dependent Claim
23 words
The digital processing system of claim 1, wherein each of said processing elements is associated with an element of a data output register.
Claim 7
Dependent Claim
199 words
A television receiving system for separating and demodulating an incoming television signal having luminance and chrominance signals, comrpising: a stopband filter for obtaining said luminance signal; a passband filter for obtaining said chrominance signal; a pair of demodulator units for obtaining two color difference signals from said chrominance signal; a pair of horizontal low pass filters for filtering each of said color difference signals, wherein each of said horizontal low pass filters has a single-instruction multiple-data processor having a number of processing elements for receiving data samples in an ordered sequence, and having an arithmetic unit associated with each processing element for performing computations, said processor also having next-neighbor communications between said processing elements, wherein said processor is programmed to perform computations to implement said filter by using said processing elements, wherein said processor is programmed to perform computations to implement said filter by using said processing elements as taps of said filter, such that said data samples are output from said processing elements in said ordered sequence; a processor control unit for providing timing and control signals to said processor; and an instruction generator for providing instruction to said processor said instructions including instructions for performing said computations.
Claim 8
Dependent Claim
199 words
A television receiving system for separating and demodulating an incoming television signal having luminance and chrominance signals, comrpising: a stopband filter for obtaining said luminance signal; a passband filter for obtaining said chrominance signal; a pair of demodulator units for obtaining two color difference signals from said chrominance signal; a pair of horizontal low pass filters for filtering each of said color difference signals, wherein each of said horizontal low pass filters has a single-instruction multiple-data processor having a number of processing elements for receiving data samples in an ordered sequence, and having an arithmetic unit associated with each processing element for performing computations, said processor also having next-neighbor communications between said processing elements, wherein said processor is programmed to perform computations to implement said filter by using said processing elements, wherein said processor is programmed to perform computations to implement said filter by using said processing elements as taps of said filter, such that said data samples are output from said processing elements in said ordered sequence; a processor control unit for providing timing and control signals to said processor; and an instruction generator for providing instruction to said processor said instructions including instructions for performing said computations.
Claim 9
Dependent Claim
24 words
The television receiving system of claim 6, and further comprising an interface for downloading said instructions from a host development system to said processor.
Claim 10
Dependent Claim
23 words
The television receiving system of claim 6, wherein each of said processing elements is associated with an element of a data input register.
Claim 11
Dependent Claim
19 words
The television receiving system of claim 6, wherein each of said processing elements is associated with a local memory.
Claim 12
Dependent Claim
23 words
The television receiving system of claim 6, wherein each of said processing elements is associated with an element of a data output register.
Claim 13
Independent Claim
231 words
A method of using a single-instruction multiple-data processor to perform horizontal digital filtering functions, comprising the steps of: associating taps of a horizontal filter function with processing elements of a single-instruction multiple-data processor, wherein the number of taps of said function determines the number of neighboring processors used to provides each sample of an in combing data signal; word-serially loading an ordered sequence of data samples of said in combing data signal into an input register of said processor, said processor having at least one processing element for each of said data samples; using each said one processing element to proves each of said data samples in parallel to realize a first intermediate result in each processing element; communicating each of said intermediate results to a neighbor processing element of each of said processing elements; storing said intermediate results in a memory associated with said neighbor processing elements; processing each of said first intermediate results, using said neighbor processing elements to realize at least one additional intermediate result; repeating said processing, communicating, and storing steps until all taps of said filter function have been realized; and communicating each of said additional intermediate results in parallel to an output register of said processor; word-serially outputting said additional intermediate results from said output register, wherein said ordered sequence is maintained for a filtered version of said signal in accordance with said filter function.
Claim 14
Independent Claim
231 words
A method of using a single-instruction multiple-data processor to perform horizontal digital filtering functions, comprising the steps of: associating taps of a horizontal filter function with processing elements of a single-instruction multiple-data processor, wherein the number of taps of said function determines the number of neighboring processors used to provides each sample of an in combing data signal; word-serially loading an ordered sequence of data samples of said in combing data signal into an input register of said processor, said processor having at least one processing element for each of said data samples; using each said one processing element to proves each of said data samples in parallel to realize a first intermediate result in each processing element; communicating each of said intermediate results to a neighbor processing element of each of said processing elements; storing said intermediate results in a memory associated with said neighbor processing elements; processing each of said first intermediate results, using said neighbor processing elements to realize at least one additional intermediate result; repeating said processing, communicating, and storing steps until all taps of said filter function have been realized; and communicating each of said additional intermediate results in parallel to an output register of said processor; word-serially outputting said additional intermediate results from said output register, wherein said ordered sequence is maintained for a filtered version of said signal in accordance with said filter function.
Claim 15
Dependent Claim
27 words
The method of claim 11 comprising the additional step of downloading, from a host development system to said processor, instructions to control said processing and communicating steps.
Claim 16
Dependent Claim
19 words
The method of claim 11 wherein said sequenced order of data samples represents one line of a television signal.
References Cited (Backward Citations)
US4141035A
Cited
US4745546A
Cited
US4602285A
Cited
US4727415A
Cited
US4769778A
Cited
US5068799A
Cited
US4683490A
Cited
US4754322A
Cited
US4821223A
Cited
US4789890A
Cited
US4843457A
Cited
US4707647A
Cited
US4775952A
Cited
US4829367A
Cited
US4994906A
Cited
US5012329A
Cited
US4918524A
Cited
US5034907A
Cited
US4984286A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |