Circuit arrangement comprising a matrix-shaped memory arrangement for digital filtration of image signals in row and column directions

Claim 1

A circuit arrangement for providing a variably adjustable time delay for a data stream of digital image data signals, comprising: a plurality of memory matrices, each memory matrix including a plurality of storage elements arranged in columns and rows, each of said storage elements comprising a three-transistor cell having overlapping write/read cycles, a separate write bit line and a separate read bit line for each column respectively connected to each cell of the respective column, and a separate write word line and a separate read word line for each row respectively connected to each cell of the respective row, a reset control signal input for receiving a reset control signal, a continuously steppable clocked row selector including a plurality of cascaded selector stages each including two mutually offset signal outputs respectively connected to a write word line and a read word line and each including a control input connected to said reset control signal input for receiving a reset control signal at an arbitrary time for setting the first stage and resetting all other stages of said row selector, an undelayed data output and a plurality of delayed data outputs, a data input for receiving an input data stream to be delayed, said data input connected to said write bit line of a first of said column and to said undelayed data output, and a plurality of amplifiers each assigned to a respective column including an input connected to a respective read bit line of the respective column and an output connected to a respective delayed data output and to said bit write line of the adjacent column, the spacing between reset pulses selected to be equal to the desired delay between said undelayed data output and the delay output of the first column; each memory matrix provided in accordance with the word width of the image data in which each of said matrices is connected to receive one data bit and offer the same time delayed at data word outputs as a respective corresponding bits of a plurality of differently time delayed output data words; an arithmetic unit connected to said matrices to receive said output data words and combining the same in accordance with a predetermined filter function such that the two smallest coefficient outputs are combined and the result combined with the next largest coefficient output, the combining being repeated with respect to increasing coefficient magnitude until the largest coefficient output has been combined; and a plurality of digital time delay elements connected between said data word outputs and said arithmetic unit for compensating different transit times through said arrangement.