Memory device with multiple processors having parallel access to the same memory area

Claim 2

A random access memory chip comprising: (a) static random access storage elements, (b) word lines and bit lines connected to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) a separate processor coupled to each of the sense amplifiers, (e) means for addressing a word line, and (f) means for providing the same single instruction at the same time to each processor of a plurality of said processors, whereby the single instruction enables the processors to carry out said single instruction in parallel on separate bits stored in the storage elements of the addressed word line.

Claim 3

A random access memory chip as defined in claim 1 in which the bit lines, storage elements and associated sense amplifiers are arranged into memory columns, the pitch of a processor and the pitch of a memory column being similar.

Claim 4

A random access memory chip as defined in claim 2 further including column decoders coupled to said memory columns and coupled to said processors for enabling data to be written to or read from at least one selected memory column and for enabling said processors to send or receive data.

Claim 5

A random access memory chip as defined in claim 2 in which: (a) each column decoder is grouped with at least one processor and memory columns associated with said at least one processor, (b) each memory array includes at least one redundant column decoder group for substitution for a non-redundant column decoder group which contains at least one of a defective processor, defective memory cell and a defective memory column.

Claim 6

A random access memory as defined in claim 1, in which the bit lines, storage elements and associated sense amplifiers are arranged into memory columns, the pitch of a processor being similar to the pitch of a small number of memory columns.

Claim 7

A random access memory chip as defined in claim 5 further including column decoders coupled to said memory columns and coupled to said processors for enabling data to be written to or read from at least one selected memory column and for enabling said processors to send or receive data.

Claim 8

A random access memory chip as defined in claim 5 in which: (a) each column decoder is grouped with at least one processor and memory column associated with said at least one processor, (b) each memory array includes at least one redundant column decoder group for substitution for a non-redundant column decoder group which contains at least one of a defective processor, defective memory cell and a defective memory column.

Claim 9

A memory chip as defined in claim 1 in which a first group of sense amplifiers is coupled to one-half of the bit lines and a second group of sense amplifiers is connected to the other half of the bit lines, said single instruction being applied to the plurality of processors coupled to each of the first and second groups of sense amplifiers, in sequence.

Claim 10

A memory chip as defined in claim 8, in which the first group of sense amplifiers is coupled to the bit lines of an array of said storage elements on one side of the processors and in which the second group of sense amplifiers is coupled to the bit lines of an array of said storage elements on the opposite side of the processors, each processor being coupled to sense amplifiers one on each side thereof, said instruction thereby activating a memory cycle of each of the two arrays of storage elements, in sequence.

Claim 11

A memory chip as defined in claim 1 including means for enabling direct storage of data bits in the storage elements by a central processing unit.

Claim 12

A memory chip as defined in claim 1 in which each processor is comprised of a dynamic logic multiplexer for use as an arithmetic logic unit.

Claim 13

A memory chip as defined in claim 1 in which each processor is comprised of a dynamic logic multiplexer having an output bus and first and second register means, means for receiving an operand from a bit line of storage elements and for applying it to an input of the multiplexer, means for receiving data bits from a first bus external to the processor and for applying the data bits to respective inputs of the register means, means for receiving data bits from the output bus of the multiplexer, and for applying the latter data bits to respective inputs of the register means, means for applying outputs of the register means to the multiplexer, and means for receiving opcode instruction data from a second bus external to the processor and for applying it to the multiplexer, whereby the multiplexer is enabled to perform an instruction on said operand and data output from the register means and to apply the result to the output bus of the multiplexer.

Claim 14

A random access memory chip as defined in claim 1 further including means for directly accessing ones or groups of storage elements via said sense amplifiers for reading from or writing to said ones or groups of storage elements.

Claim 15

A memory chip as defined in claim 1 in which each processor is comprised of first and second dynamic logic multiplexers having corresponding first and second output buses, first and second register means, the first register means having an input coupled to the first output bus, the second register means having an input coupled to the second output bus, outputs of both register means being coupled to inputs of both multiplexers, means in each multiplexer for receiving an operand from a bit line of storage elements, a first external bus, means for receiving opcode instruction bits from the first external bus and for applying separate opcode instructions.

Claim 16

A memory chip as defined in claim 1, in which the sense amplifiers and processors are all physically located on one side of an array of memory elements.

Claim 17

A memory chip as defined in claim 1, in which the one-half the sense amplifiers and corresponding one-half the processors are physically located on one side of a first array of memory elements, the sense amplifiers located on one side of the array being coupled to odd numbered bit lines, and the sense amplifiers located on another side of the array being coupled to even numbered bit lines.

Claim 18

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) a first group of sense amplifiers being coupled to one-half of the bit lines and a second group of sense amplifiers being coupled to the other half of the bit lines, said single instruction being applied to the plural processors connected to each of the first and second groups of sense amplifiers in sequence.

Claim 19

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) a first group of sense amplifiers being coupled to one-half of the bit lines and a second group of sense amplifiers being coupled to the other half of the bit lines, said single instruction being applied to the plural processors connected to each of the first and second groups of sense amplifiers in sequence.

Claim 20

A memory chip as defined in claim 17 in which the first group of sense amplifiers is coupled to the bit lines of an array of said storage elements on one side of the processors and in which the second group of sense amplifiers is coupled to the bit lines of an array of said storage elements on the opposite side of the processors, each processor being coupled to sense amplifiers one on each side thereof, said instruction thereby activating a memory cycle of each of the two arrays of storage elements, in sequence.

Claim 21

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and including (g) means for enabling direct storage of data bits in the storage elements by a central processing unit.

Claim 22

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and including (g) means for enabling direct storage of data bits in the storage elements by a central processing unit.

Claim 23

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which each processor is comprised of a dynamic logic multiplexer for use as an arithmetic logic unit.

Claim 24

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which each processor is comprised of a dynamic logic multiplexer for use as an arithmetic logic unit.

Claim 25

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which each multiplexer is comprised of a dynamic logic multiplexer having an output bus and first and second register means, means for receiving an operand from a bit line of storage elements and for applying it to an input of the multiplexer, means for receiving data bits from a first bus external to the processor and for applying them to respective inputs of the register means, means for receiving data bits from the output bus of the processor, and for applying them to respective inputs of the register means, means for applying outputs of the register means to the multiplexer, and means for receiving opcode instruction data from a second bus external to the processor and for applying it to the multiplexer, whereby the multiplexer is enabled to perform an instruction on said operand and data output from the register means and to apply the result to the output bus of the multiplexer.

Claim 26

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which each multiplexer is comprised of a dynamic logic multiplexer having an output bus and first and second register means, means for receiving an operand from a bit line of storage elements and for applying it to an input of the multiplexer, means for receiving data bits from a first bus external to the processor and for applying them to respective inputs of the register means, means for receiving data bits from the output bus of the processor, and for applying them to respective inputs of the register means, means for applying outputs of the register means to the multiplexer, and means for receiving opcode instruction data from a second bus external to the processor and for applying it to the multiplexer, whereby the multiplexer is enabled to perform an instruction on said operand and data output from the register means and to apply the result to the output bus of the multiplexer.

Claim 27

A memory chip as defined in claim 21, including means in each processor for writing a data bit from the bus external to the multiplexer.

Claim 28

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which each processor is connected to a separate group of sense amplifiers, each processor being capable of processing word lengths of N bits per word, each group of sense amplifiers having N sense amplifiers connected to respective N bit lines, each sense amplifier contributing 1 bit to an N bit word processed by a corresponding processor.

Claim 29

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which each processor is connected to a separate group of sense amplifiers, each processor being capable of processing word lengths of N bits per word, each group of sense amplifiers having N sense amplifiers connected to respective N bit lines, each sense amplifier contributing 1 bit to an N bit word processed by a corresponding processor.

Claim 30

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and further including (g) means for directly accessing ones of groups of storage elements via said sense amplifiers for reading from or writing to said ones or groups of storage elements.

Claim 31

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and further including (g) means for directly accessing ones of groups of storage elements via said sense amplifiers for reading from or writing to said ones or groups of storage elements.

Claim 32

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which the separate processors are multiplexed to each of the sense amplifiers to which they are connected.

Claim 33

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which the separate processors are multiplexed to each of the sense amplifiers to which they are connected.

Claim 34

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which each processor is comprised of first and second dynamic logic multiplexers having corresponding first and second output buses, first and second register means, the first register means having an input coupled to the first output bus, the second register means having an input coupled to the second output bus, outputs of both register means being coupled to inputs of both multiplexers, means in each multiplexer for receiving an operand from a bit line of storage elements, a first external bus, means for receiving opcode instruction bits from the first external bus and for applying separate opcode instructions.

Claim 35

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which each processor is comprised of first and second dynamic logic multiplexers having corresponding first and second output buses, first and second register means, the first register means having an input coupled to the first output bus, the second register means having an input coupled to the second output bus, outputs of both register means being coupled to inputs of both multiplexers, means in each multiplexer for receiving an operand from a bit line of storage elements, a first external bus, means for receiving opcode instruction bits from the first external bus and for applying separate opcode instructions.

Claim 36

A memory chip as defined in claim 26 further including a second bus external to each processor, bidirectional coupler means coupling the second external bus to said second output bus of said second multiplexer, and means coupling said second output bus of said second multiplexer to a corresponding bit line through a corresponding sense amplifier.

Claim 37

A memory chip as defined in claim 26 in which the coupling means is comprised of an addressable bidirectional coupler.

Claim 38

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line and (g) in which the sense amplifiers and processors are all physically located on one side of an array of memory elements.

Claim 39

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line and (g) in which the sense amplifiers and processors are all physically located on one side of an array of memory elements.

Claim 40

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which one half of the sense amplifiers and corresponding one half the processors are physically located on respective opposite sides of a first array of memory elements, the sense amplifiers located on one side of the array being connected to odd numbered bit lines, and the sense amplifiers located on the other side of the array being connected to even numbered bit lines.

Claim 41

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which one half of the sense amplifiers and corresponding one half the processors are physically located on respective opposite sides of a first array of memory elements, the sense amplifiers located on one side of the array being connected to odd numbered bit lines, and the sense amplifiers located on the other side of the array being connected to even numbered bit lines.

Claim 42

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which the number of sense amplifiers connected to each processor is no more than eight.

Claim 43

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each coupled to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, and (g) in which the number of sense amplifiers connected to each processor is no more than eight.

Claim 44

A memory chip as defined in claim 31 in which the number of sense amplifiers connected to each processor is no more than four.

Claim 45

A random access memory chip comprising: (a) static random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers coupled to corresponding bit lines, (d) plural processors, each processor being coupled to a corresponding sense amplifier, (e) a plurality of address pins, (f) means for demultiplexing word line address signals and processor instructions received via the same plurality of address pins, and (g) means for providing a single instruction of said processor instructions to plural ones of said processors at the same time via said address pins, whereby instructions carried via said address pins are received by said plural processors to carry out said single instruction in parallel on separate bits stored in the storage elements of said word line addressed via said address pins.

Claim 46

A random access memory chip comprising: (a) static random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers coupled to corresponding bit lines, (d) plural processors, each processor being coupled to a corresponding sense amplifier, (e) a plurality of address pins, (f) means for demultiplexing word line address signals and processor instructions received via the same plurality of address pins, and (g) means for providing a single instruction of said processor instructions to plural ones of said processors at the same time via said address pins, whereby instructions carried via said address pins are received by said plural processors to carry out said single instruction in parallel on separate bits stored in the storage elements of said word line addressed via said address pins.

Claim 47

A random access memory chip as defined in claim 33 in which said means for demultiplexing further provides demultiplexed memory row and column address signals to row and column decoders of said memory chip.

Claim 48

A random access memory chip as defined in claim 33, and further including decoders for receiving and decoding bit line addresses and for enabling data to be written to corresponding processors, the pitch of each processor being similar to the pitch of a bit line.

Claim 49

A random access memory as defined in claim 35 in which separate decoders receive and decode bit line addresses and enable data to be written for a group of bit lines, and further including redundant ones of said decoders for substitution of said separate decoders.

Claim 50

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers coupled to corresponding bit lines, (d) plural processors, each processor being coupled to plural sense amplifiers for processing bits sensed by said plural sense amplifiers coupled thereto, (e) a plurality of address pins, (f) means for demultiplexing word line address signals and processor instructions received via the same plurality of address pins, and (g) means for providing a single instruction of said processor instructions to plural ones of said processors at the same time via said address pins, whereby instructions carried via said address pins are received by said plural processors to carry out said instructions in parallel on separate bits stored in the storage elements of said word line addressed via said address pins.

Claim 51

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines coupled to the storage elements, (c) plural sense amplifiers coupled to corresponding bit lines, (d) plural processors, each processor being coupled to plural sense amplifiers for processing bits sensed by said plural sense amplifiers coupled thereto, (e) a plurality of address pins, (f) means for demultiplexing word line address signals and processor instructions received via the same plurality of address pins, and (g) means for providing a single instruction of said processor instructions to plural ones of said processors at the same time via said address pins, whereby instructions carried via said address pins are received by said plural processors to carry out said instructions in parallel on separate bits stored in the storage elements of said word line addressed via said address pins.

Claim 52

A random access memory chip as defined in claim 37 in which said means for demultiplexing further provides demultiplexed memory row and column address signals to row and column decoders of said memory chip.

Claim 53

A random access memory as defined in claim 37 in which separate decoders receive and decode bit line addresses and enable data to be written for a group of bit lines, and further including redundant ones of said decoders for substitution of said separate decoders.

Claim 54

A random access memory chip comprising: (a) static random access storage elements, (b) word lines and bit lines connected to the storage elements, (c) said storage elements and word and bit lines being grouped into arrays, (d) processors being disposed between a pair of said arrays, with one processor allocated to corresponding bit lines of said pair of arrays, (e) each processor being coupled via corresponding sense amplifiers to corresponding bit lines of said pair of arrays, (f) means for addressing a word line of one of said pair of arrays, and (g) means for providing a single instruction to said processor elements, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of only said addressed one of said pair of arrays, and subsequently on separate bits stored in the storage elements of another one of said addressed one of said pair of arrays.

Claim 55

A random access memory chip comprising: (a) static random access storage elements, (b) word lines and bit lines connected to the storage elements, (c) said storage elements and word and bit lines being grouped into arrays, (d) processors being disposed between a pair of said arrays, with one processor allocated to corresponding bit lines of said pair of arrays, (e) each processor being coupled via corresponding sense amplifiers to corresponding bit lines of said pair of arrays, (f) means for addressing a word line of one of said pair of arrays, and (g) means for providing a single instruction to said processor elements, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of only said addressed one of said pair of arrays, and subsequently on separate bits stored in the storage elements of another one of said addressed one of said pair of arrays.

Claim 56

A random access memory chip as defined in claim 40 including means for powering only one of said pair of arrays in which the word lines are being addressed.

Claim 57

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines connected to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each connected to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, (g) the bit lines, storage elements and sense amplifiers being arranged in memory columns, and (h) the pitch of a processor being similar to the pitch of a small number of memory columns.

Claim 58

A random access memory chip comprising: (a) dynamic random access storage elements, (b) word lines and bit lines connected to the storage elements, (c) plural sense amplifiers, each one coupled to corresponding bit lines, (d) plural processors each connected to plural sense amplifiers for processing bits sensed by said sense amplifiers, (e) means for addressing a word line, (f) means for providing a single instruction to each of said processors, whereby the processors are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the word line, (g) the bit lines, storage elements and sense amplifiers being arranged in memory columns, and (h) the pitch of a processor being similar to the pitch of a small number of memory columns.

Claim 59

A random access memory chip as defined in claim 42 in which: (a) each column decoder is grouped with at least one processor and memory columns associated with said at least one processor, (b) each memory array includes at least one redundant column decoder group for substitution for a non-redundant column decoder group which contains at least one of a defective processor, defective memory cell and a defective memory column.