Universal clock generator using delay lock loop

Claim 2

A clock generator comprising: a delay lock loop receiving an input clock signal having an input clock frequency and generating a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal; a sequencer coupled to the delay lock loop to receive the delayed clock signals and selecting one of the delayed clock signals at any moment according to a predetermined sequence to generate an output clock signal having an output clock frequency corresponding to the predetermined sequence; and a token generator coupled to receive the output clock signal from the sequencer and generating control signals for controlling the sequencer, the control signals controlling the sequencer to select one of the delayed clock signals at every cycle of the output clock signal according to the predetermined sequence.

Claim 3

The clock generator of claim 1 , wherein the token generator comprises a wrap-around shift register clocked by the output clock signal as a rotating clock and generating the control signals.

Claim 4

The clock generator of claim 2 , wherein the wraparound shift register comprises a plurality of D-type flip flops connected in series, one of the D-type flip flops being set and the remaining D-type flip flops being reset in response to the clock generator being powered on.

Claim 5

The clock generator of claim 1 , wherein the sequencer comprises a multiplexer receiving the delayed clock signals and selecting one of the delayed clock signals at any moment as the output clock signal according to the predetermined sequence in response to the control signals.

Claim 6

The clock generator of claim 1 , further comprising a divide-by-2 circuit coupled to receive the output clock signal from the sequencer for reducing the output clock frequency by half and adjusting a duty cycle of the output clock signal to fifty percent.

Claim 7

The clock generator of claim 5 , wherein the divide-by-2 circuit comprises a D-type flip flop clocked by the output clock signal, an inverting output of the D-type flip flop being coupled to a data input of the D-type flip flop.

Claim 8

A clock generator comprising: a delay lock loop receiving an input clock signal having an input clock frequency and generating a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal; a first sequencer coupled to the delay lock loop to receive the delayed clock signals and selecting one of the delayed clock signals at any moment according to a first sequence to generate a first output clock signal having a first output clock frequency corresponding to the first sequence; a second sequencer coupled to the delay lock loop to receive the delayed clock signals and selecting one of the delayed clock signals at any moment according to a second sequence to generate a second output clock signal having a second output clock frequency corresponding to the second sequence; a first token generator coupled to receive the first output clock signal from the first sequencer and Generating first control signals for controlling the first sequencer, the first control signals controlling the first sequencer to select one of the delayed clock signals at every cycle of the first output clock signal according to the first sequence; and a second token generator coupled to receive the second output clock signal from the second sequencer and generating second control signals for controlling the second sequencer, the second control signals controlling the second sequencer to select one of the delayed clock signals at every cycle of the second output clock signal according to the second sequence.

Claim 9

A clock generator comprising: a delay lock loop receiving an input clock signal having an input clock frequency and generating a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal; a first sequencer coupled to the delay lock loop to receive the delayed clock signals and selecting one of the delayed clock signals at any moment according to a first sequence to generate a first output clock signal having a first output clock frequency corresponding to the first sequence; a second sequencer coupled to the delay lock loop to receive the delayed clock signals and selecting one of the delayed clock signals at any moment according to a second sequence to generate a second output clock signal having a second output clock frequency corresponding to the second sequence; a first token generator coupled to receive the first output clock signal from the first sequencer and Generating first control signals for controlling the first sequencer, the first control signals controlling the first sequencer to select one of the delayed clock signals at every cycle of the first output clock signal according to the first sequence; and a second token generator coupled to receive the second output clock signal from the second sequencer and generating second control signals for controlling the second sequencer, the second control signals controlling the second sequencer to select one of the delayed clock signals at every cycle of the second output clock signal according to the second sequence.

Claim 10

The clock generator of claim 7 , wherein: the first token generator comprises a first wrap-around shift register clocked by the first output clock signal as a first rotating clock and generating the first control signals; and the second token generator comprises a second wrap-around shift register clocked by the second output clock signal as a second rotating clock and generating the second control signals.

Claim 11

The clock generator of claim 8 , wherein: the first shift register comprises a first plurality of D-type flip flops connected in series, one of the first D-type flip flops being set and the remaining first D-type flip flops being reset in response to the clock generator being powered on; and the second shift register comprises a second plurality of D-type flip flops connected in series, one of the second D-type flip flops being set and the remaining second D-type flip flops being reset in response to the clock generator being powered on.

Claim 12

The clock generator of claim 7 , wherein: the first sequencer comprises a first multiplexer receiving the delayed clock signals and selecting one of the delayed clock signals at any moment as the first output clock signal according to the first sequence in response to the first control signals; and the second sequencer comprises a second multiplexer receiving the delayed clock signals and selecting one of the delayed clock signals at any moment as the second output clock signal according to the second sequence in response to the second control signals.

Claim 13

The clock generator of claim 7 , further comprising: a first divide-by-2 circuit coupled to receive the first output clock signal from the first sequencer for reducing the first output clock frequency by half and adjusting a duty cycle of the first output clock signal to fifty percent; and a second divide-by-2 circuit coupled to receive the second output clock signal from the second sequencer for reducing the second output clock frequency by half and adjusting a duty cycle of the second output clock signal to fifty percent.

Claim 14

The clock generator of claim 11 , wherein: the first divide-by-2 circuit comprises a first D-type flip flop clocked by the first output clock signal, an inverting output of the first D-type flip flop being coupled to a data input of the first D-type flip flop; and the second divide-by-2 circuit comprises a second D-type flip flop clocked by the second output clock signal, an inverting output of the second D-type flip flop being coupled to a data input of the second D-type flip flop.

Claim 17

The method of claim 13 , further comprising reducing the output clock frequency by half and adjusting a duty cycle of the output clock signal to fifty percent.

Claim 20

The clock generator of claim 15 , further comprising: reducing the first output clock frequency by half and adjusting a duty cycle of the first output clock signal to fifty percent; and reducing the second output clock frequency by half and adjusting a duty cycle of the second output clock signal to fifty percent.

Claim 21

A clock generator comprising: delay lock loop means for receiving an input clock signal having an input clock frequency and generating a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal; sequencer means for receiving the delayed clock signals and selecting one of the delayed clock signals at any moment according to a predetermined sequence to generate an output clock signal having an output clock frequency corresponding to the predetermined sequence; and token generator means for receiving the output clock signal from the sequencer means and for generating control signals for controlling the sequencer means, the control signals controlling the sequencer means to select one of the delayed clock signals at every cycle of the output clock signal according to the predetermined sequence.

Claim 22

A clock generator comprising: delay lock loop means for receiving an input clock signal having an input clock frequency and generating a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal; sequencer means for receiving the delayed clock signals and selecting one of the delayed clock signals at any moment according to a predetermined sequence to generate an output clock signal having an output clock frequency corresponding to the predetermined sequence; and token generator means for receiving the output clock signal from the sequencer means and for generating control signals for controlling the sequencer means, the control signals controlling the sequencer means to select one of the delayed clock signals at every cycle of the output clock signal according to the predetermined sequence.

Claim 23

The clock generator of claim 17 , further comprising frequency divider means coupled to the sequencer means for reducing the output clock frequency by half and adjusting a duty cycle of the output clock signal to fifty percent.