Plurality of distinct multiplexers that operate as a single multiplexer

Claim 2

A multiplexing arrangement comprising: a set of data inputs; a first multiplexer coupled to a first subset of the set of data inputs and having a first data output; a second multiplexer coupled to a second subset of the set of data inputs and having a second data output, wherein only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time; and a logic gate coupled to the first and second data outputs, the logic gate synthesizing an output of the multiplexing arrangement in response to values of the first and second data outputs such that the multiplexing arrangement operates as a single multiplexer; wherein each of the first and second multiplexers comprises a first input buffer and a first pass gate coupled in series between a first data input and a common node; a second input buffer and a second pass gate coupled in series between a second data input and the common node; a biasing circuit coupled to the common node and a supply voltage, the biasing circuit being operative to bias the common node to the supply voltage when neither pass gate is switched on to pass data from its corresponding input buffer to the common node; and an output buffer coupled to the common node, the output buffer operative to output an output signal to a data output in response to a voltage of the common node.

Claim 3

The multiplexing arrangement of claim 1 wherein the logic gate performs a logical OR operation.

Claim 4

A multiplexing arrangement comprising: a set of data inputs a first multiplexer coupled to a first subset of the set of data inputs and having a first data output; a second multiplexer coupled to a second subset of the set of data inputs and having a second data output, wherein only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time; wherein each of the first and second multiplexers comprises a first data path comprising: a first input buffer and a first pass gate coupled in series between a first data input and a first common node; and a first biasing circuit coupled to the first common node and a supply voltage, the biasing circuit being operative to bias the first common node to the supply voltage when the first pass gate is switched off; a second data path comprising: a second input buffer and a second pass gate coupled in series between a second data input and a second common node; a second biasing circuit coupled to the second common node and a supply voltage, the biasing circuit being operative to bias the common node to the supply voltage when the second pass gate is switched off; and an output buffer coupled to the first and second common nodes, the output buffer operative to output an output signal to a data output in response to voltages at the first and second common nodes.

Claim 5

A multiplexing arrangement comprising: a set of data inputs a first multiplexer coupled to a first subset of the set of data inputs and having a first data output; a second multiplexer coupled to a second subset of the set of data inputs and having a second data output, wherein only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time; wherein each of the first and second multiplexers comprises a first data path comprising: a first input buffer and a first pass gate coupled in series between a first data input and a first common node; and a first biasing circuit coupled to the first common node and a supply voltage, the biasing circuit being operative to bias the first common node to the supply voltage when the first pass gate is switched off; a second data path comprising: a second input buffer and a second pass gate coupled in series between a second data input and a second common node; a second biasing circuit coupled to the second common node and a supply voltage, the biasing circuit being operative to bias the common node to the supply voltage when the second pass gate is switched off; and an output buffer coupled to the first and second common nodes, the output buffer operative to output an output signal to a data output in response to voltages at the first and second common nodes.

Claim 6

The multiplexing arrangement of claim 3 wherein the first data path of at least one of the first and second multiplexers further comprises a third input buffer and a third pass gate coupled in series between a third data input and the first common node.

Claim 7

A multiplexing arrangement comprising: a set of data inputs for coupling to receive data signals; a first multiplexer coupled to a first subset of the set of data inputs and having a first data output, the first data output being biased to a known state when the first multiplexer is not selected to output data; a second multiplexer coupled to a second subset of the set of data inputs and having a second data output, the second data output being biased to a known state when the second multiplexer is not selected to output data, wherein only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time; and a logic gate coupled to the first and second data outputs, the logic gate synthesizing an output of the multiplexing arrangement in response to values of the first and second data outputs such that the multiplexing arrangement operates as a single multiplexer.

Claim 8

A multiplexing arrangement comprising: a set of data inputs for coupling to receive data signals; a first multiplexer coupled to a first subset of the set of data inputs and having a first data output, the first data output being biased to a known state when the first multiplexer is not selected to output data; a second multiplexer coupled to a second subset of the set of data inputs and having a second data output, the second data output being biased to a known state when the second multiplexer is not selected to output data, wherein only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time; and a logic gate coupled to the first and second data outputs, the logic gate synthesizing an output of the multiplexing arrangement in response to values of the first and second data outputs such that the multiplexing arrangement operates as a single multiplexer.

Claim 9

The multiplexing arrangement of claim 5, wherein each of the first and second multiplexers comprises: a first input buffer and a first pass gate coupled in series between a first data input and a common node; a second input buffer and a second pass gate coupled in series between a second data input and the common node; a biasing circuit coupled to the common node and a supply voltage, the biasing circuit being operative to bias the common node to the supply voltage when neither pass gate is switched on to pass data from its corresponding input buffer to the common node; and an output buffer coupled to the common node, the output buffer operative to output an output signal to a data output in response to a voltage of the common node.

Claim 10

The multiplexing arrangement of claim 5, wherein each of the first and second multiplexers comprises: a first data path comprising: a first input buffer and a first pass gate coupled in series between a first data input and a first common node; and a first biasing circuit coupled to the first common node and a supply voltage, the biasing circuit being operative to bias the first common node to the supply voltage when the first pass gate is switched off; a second data path comprising: a second input buffer and a second pass gate coupled in series between a second data input and a second common node; a second biasing circuit coupled to the second common node and a supply voltage, the biasing circuit being operative to bias the common node to the supply voltage when the second pass gate is switched off; and an output buffer coupled to the first and second common nodes, the output buffer operative to output an output signal to a data output in response to voltages at the first and second common nodes.

Claim 11

The multiplexing arrangement of claim 7 wherein the first data path of at least one of the first and second multiplexers further comprises a third input buffer and a third pass gate coupled in series between a third data input and the first common node.

Claim 12

The multiplexing arrangement of claim 5 wherein the logic gate performs a logical OR operation.

Claim 15

The method of claim 10 wherein the step of synthesizing an output signal comprises performing a logical OR function using the outputs of the first and second multiplexers.