US6404839B1
Expired / Lapsed
US
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Selectable clock divider circuit with a 50% duty cycle clock
Assignee: Oracle America Inc
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Filing: 2001-02-28
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Granted: 2002-06-11
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Expires: 2021-02-28
Abstract
Abstract A clock divider circuit having a fifty per cent duty cycle and multiple integer ratios for dividing an input clock signal. In one embodiment, a clock divider circuit may include a chain of serially-coupled flip-flops. The chain may include at least a first and a second flip-flop, both of which may be triggered by a first edge of an input clock signal. A third flip-flop, coupled to (but not part of) the chain may be configured to be triggered by a second edge of the input clock signal. The third flip-flop may be coupled to an output circuit. In addition to receiving the output signal from the third flip-flop, the output circuit may also receive signals from the chain of serially-coupled flip-flops. The output circuit may drive a second clock signal, which may be produced by dividing the first clock signal based upon the signals it receives. The first clock signal may be divided by an even or an odd integer ratio, or may be divided by an integer ratio (e.g. 2.5), although clock signals produced based on a decimal ratio may have a duty cycle that is not fifty per cent.
Inventors
- 👤 Wai Fong
- 👤 Jyh-Ming Jong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:26
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/502; H03K23/505; H03K21/00; H03K21/08; H03K21/10
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
95 words
A clock divider comprising: a chain of serially coupled flip-flops including at least a first flip-flop and a second flip-flop, wherein said first flip-flop and said second flip-flop are triggered by a first clock edge of an input clock signal; a third flip-flop coupled to said chain of serially coupled flip-flops, wherein said third flip-flop is triggered by a second clock edge of said input clock signal; and a circuit coupled to said third flip-flop, wherein said third flip-flop is configured to receive an input signal dependent upon a combination of inputs to said circuit.
Claim 2
Dependent Claim
95 words
A clock divider comprising: a chain of serially coupled flip-flops including at least a first flip-flop and a second flip-flop, wherein said first flip-flop and said second flip-flop are triggered by a first clock edge of an input clock signal; a third flip-flop coupled to said chain of serially coupled flip-flops, wherein said third flip-flop is triggered by a second clock edge of said input clock signal; and a circuit coupled to said third flip-flop, wherein said third flip-flop is configured to receive an input signal dependent upon a combination of inputs to said circuit.
Claim 3
Dependent Claim
28 words
The clock divider as recited in claim 1 , wherein an output clock signal of said clock divider is dependent upon an output signal from said third flip-flop.
Claim 4
Dependent Claim
38 words
The clock divider as recited in claim 2 , further comprising and output circuit, said output circuit configured to receive said output signal from said third flip-flop and at least one signal from said chain of serially-coupled flip-flops.
Claim 5
Dependent Claim
36 words
The clock divider as recited in claim 3 , wherein said output circuit is configured to drive an output clock signal, said output clock signal produced by dividing said input clock signal by a predetermined ratio.
Claim 6
Dependent Claim
31 words
The clock divider as recited in claim 4 , wherein said predetermined ratio is selected from a plurality of ratios, said plurality of ratios including both odd and even integer values.
Claim 7
Dependent Claim
22 words
The clock divider as recited in claim 5 , wherein said clock divider includes a selector circuit for selecting said predetermined ratio.
Claim 8
Dependent Claim
27 words
The clock divider as recited in claim 6 , wherein said input clock signal and said output clock signal each have a fifty per cent duty cycle.
Claim 9
Dependent Claim
17 words
The clock divider as recited in claim 1 , wherein said circuit is a combinational logic circuit.
Claim 10
Dependent Claim
14 words
The clock divider as recited in claim 1 , wherein said flip-flops are D-flip-flops.
Claim 11
Dependent Claim
27 words
The clock divider as recited in claim 1 , wherein said first clock edge is a positive edge and said second clock edge is a negative edge.
Claim 12
Dependent Claim
27 words
The clock divider as recited in claim 1 , wherein said first clock edge is a negative edge, and said second clock edge is a positive edge.
Claim 13
Dependent Claim
29 words
The clock divider as recited in claim 1 , wherein said circuit is configured to receive one or more input signals from a source external to said clock divider.
Claim 14
Dependent Claim
28 words
The clock divider as recited in claim 1 , wherein said input circuit is configured to receive one or more input signals from said chain of serially-coupled flip-flops.
Claim 15
Dependent Claim
102 words
A computer system comprising: a clock divider, said clock divider including: a chain of serially coupled flip-flops including at least a first flip-flop and a second flip-flop, wherein said first flip-flop and said second flip-flop are triggered by a first clock edge of an input clock signal; a third flip-flop coupled to said chain of serially coupled flip-flops, wherein said third flip-flop is triggered by a second clock edge of said input clock signal; and a circuit coupled to said third flip-flop, wherein said third flip-flop is configured to receive an input signal dependent upon a combination of inputs to said circuit.
Claim 16
Dependent Claim
102 words
A computer system comprising: a clock divider, said clock divider including: a chain of serially coupled flip-flops including at least a first flip-flop and a second flip-flop, wherein said first flip-flop and said second flip-flop are triggered by a first clock edge of an input clock signal; a third flip-flop coupled to said chain of serially coupled flip-flops, wherein said third flip-flop is triggered by a second clock edge of said input clock signal; and a circuit coupled to said third flip-flop, wherein said third flip-flop is configured to receive an input signal dependent upon a combination of inputs to said circuit.
Claim 17
Dependent Claim
28 words
The computer system as recited in claim 14 , wherein an output clock signal of said clock divider is dependent upon an output signal from said third flip-flop.
Claim 18
Dependent Claim
26 words
The computer system as recited in claim 15 further comprising and output circuit, said output circuit configured to receive said output signal from said third flip-flop.
Claim 19
Dependent Claim
36 words
The computer system as recited in claim 16 , wherein said output circuit is configured to drive an output clock signal, said output clock signal produced by dividing said input clock signal by a predetermined ratio.
Claim 20
Dependent Claim
31 words
The computer system as recited in claim 17 , wherein said predetermined ratio is selected from a plurality of ratios, said plurality of ratios including both odd and even integer values.
Claim 21
Dependent Claim
22 words
The computer system as recited in claim 18 , wherein said clock divider includes a selector circuit for selecting said predetermined ratio.
Claim 22
Dependent Claim
27 words
The computer system as recited in claim 19 , wherein said input clock signal and said output clock signal each have a fifty per cent duty cycle.
Claim 23
Dependent Claim
17 words
The computer system as recited in claim 14 , wherein said circuit is a combinational logic circuit.
Claim 24
Dependent Claim
14 words
The computer system as recited in claim 14 , wherein said flip-flops are D-flip-flops.
Claim 25
Dependent Claim
27 words
The computer system as recited in claim 14 , wherein said first clock edge is a positive edge and said second clock edge is a negative edge.
Claim 26
Dependent Claim
27 words
The computer system as recited in claim 14 , wherein said first clock edge is a negative edge, and said second clock edge is a positive edge.
Claim 27
Dependent Claim
29 words
The computer system as recited in claim 14 , wherein said circuit is configured to receive one or more input signals from a source external to said clock divider.
Claim 28
Dependent Claim
27 words
The computer system as recited in claim 14 , wherein said circuit is configured to receive one or more input signals from said chain of serially-coupled flip-flops.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-10 | 2005-12-10 | 2006-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-10 | 2009-12-10 | 2010-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-10 | 2013-12-10 | 2014-06-11 | $7700.00 | Window Closed / Lapsed |