US6424691B1
Expired / Lapsed
US
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Phase locked loop clock divider utilizing a high speed programmable linear feedback shift register
Assignee: National Semiconductor Corp
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Filing: 2001-09-21
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Granted: 2002-07-23
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Expires: 2021-09-21
Abstract
Abstract An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register. A plurality of pre-load flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop units and multiplexers. The PLFF circuits hold two initial LFSR sequence values. A load enable signal to the PLFF multiplexers and LFSR multiplexers is high for two input clock cycles. The present invention is capable of operating at high frequencies due to a shortened critical timing path.
Inventors
- 👤 Karthik R. Neravetla
- 👤 Steven J. Kommrusch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:56
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54; H03K23/64; H03K23/66; H03K23/665
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
134 words
A linear feedback shift register of the type comprising a plurality of linear feedback shift register (LFSR) flip flop circuits and a plurality of linear feedback shift register (LFSR) multiplexers alternately coupled together, where an input of each LFSR flip flop circuit is coupled to an output of an LFSR multiplexer, and where an output of each LFSR flip flop circuit may be provided to an input of an LFSR multiplexer, said linear feedback shift register comprising: a plurality of pre-load flip flop (PLFF) circuits and a plurality of pre-load flip flop (PLFF) multiplexers alternately coupled together, where an input of each PLFF flip flop circuit is coupled to an output of a PLFF multiplexer, and where an output of each PLFF flip flop circuit is coupled to an input of an LFSR multiplexer.
Claim 2
Dependent Claim
134 words
A linear feedback shift register of the type comprising a plurality of linear feedback shift register (LFSR) flip flop circuits and a plurality of linear feedback shift register (LFSR) multiplexers alternately coupled together, where an input of each LFSR flip flop circuit is coupled to an output of an LFSR multiplexer, and where an output of each LFSR flip flop circuit may be provided to an input of an LFSR multiplexer, said linear feedback shift register comprising: a plurality of pre-load flip flop (PLFF) circuits and a plurality of pre-load flip flop (PLFF) multiplexers alternately coupled together, where an input of each PLFF flip flop circuit is coupled to an output of a PLFF multiplexer, and where an output of each PLFF flip flop circuit is coupled to an input of an LFSR multiplexer.
Claim 3
Dependent Claim
45 words
A linear feedback shift register as claimed in claim 1 wherein said each of said plurality of PLFF multiplexers has a first input coupled to one bit of an input register value and a second input coupled to another bit of said input register value.
Claim 4
Dependent Claim
105 words
A linear feedback shift register as claimed in claim 2 having n bits and a polynomial equation of R[m]+R[p] where m is an integer less than n and where p is an integer less than n wherein a PLFF multiplexer that is coupled to a first PLFF flip flop circuit has one input coupled to an input register value bit equal to N[ 0 ] when a load enable signal coupled to said PLFF multiplexer is low and another input coupled to an input register value bit equal to N[m] XNORed with N[p] when said load enable signal coupled to said PLFF multiplexer is high.
Claim 5
Dependent Claim
64 words
A linear feedback shift register as claimed in claim 3 comprising a circuit in a feedback path of said linear feedback shift register, wherein said circuit is capable of performing an exclusive NOR function on an output signal of one of said plurality of LFSR flip flop circuits and on an output signal of another one of said plurality of LFSR flip flop circuits.
Claim 6
Dependent Claim
97 words
A linear feedback shift register as claimed in claim 2 having six (6) bits and a polynomial equation of R[ 5 ]+R[ 4 ] wherein a PLFF multiplexer that is coupled to a first PLFF flip flop circuit has one input coupled to an input register value bit equal to N[ 0 ] when a load enable signal coupled to said PLFF multiplexer is low and another input coupled to an input register value bit equal to N[ 4 ] XNORed with N[ 5 ] when said load enable signal coupled to said PLFF multiplexer is high.
Claim 7
Dependent Claim
65 words
A linear feedback shift register as claimed in claim 5 comprising a circuit in a feedback path of said linear feedback shift register, wherein said circuit is capable of performing an exclusive NOR function on an output signal of an LFSR 4 flip flop circuit and on an output signal of an LFSR 3 flip flop circuit of said plurality of LFSR flip flop circuits.
Claim 8
Dependent Claim
94 words
A linear feedback shift register as claimed in claim 6 wherein said circuit in said feedback path comprises: a multiplexer having a first input connected to an output of said LFSR 3 flip flop circuit, and having a second input connected to an inverted version of said output of said LFSR 3 flip flop circuit, and having an enable input coupled to an output of said LFSR 4 flip flop circuit; and a flip flop circuit having an input coupled to an output of said multiplexer and an output coupled to said feedback path.
Claim 9
Dependent Claim
44 words
A linear feedback shift register as claimed in claim 3 wherein each LFSR multiplexer and each PLFF multiplexer has an enable signal input line connected to a load enable circuit that provides a load enable signal that is high for two input clock cycles.
Claim 10
Dependent Claim
63 words
A linear feedback shift register as claimed in claim 8 wherein said plurality of pre-load flip flop (PLFF) circuits hold a first linear feedback shift register (LFSR) sequence value when said load enable signal is low; and wherein said plurality of pre-load flip flop (PLFF) circuits hold a second linear feedback shift register (LFSR) sequence value when said load enable signal is high.
Claim 11
Dependent Claim
71 words
A linear feedback shift register as claimed in claim 9 capable of operating in a frequency range from approximately six hundred million cycles per second (600 MHz) to approximately nine hundred million cycles per second (900 MHz) where said linear feedback shift register utilizes 0.18 micron process technology and standard flip flop circuits for said pre-load flip flop (PLFF) circuits and for said linear feedback shift register (LFSR) flip flop circuits.
Claim 12
Dependent Claim
76 words
A linear feedback shift register as claimed in claim 9 capable of operating in a frequency range from approximately one billion two hundred million cycles per second (1.2 GHz) to approximately one billion five hundred million cycles per second (1.5 GHz) where said linear feedback shift register utilizes 0.18 micron process technology and custom designed flip flop circuits for said pre-load flip flop (PLFF) circuits and for said linear feedback shift register (LFSR) flip flop circuits.
Claim 13
Dependent Claim
142 words
A phase locked loop clock divider circuit comprising a linear feedback shift register of the type comprising a plurality of linear feedback shift register (LFSR) flip flop circuits and a plurality of linear feedback shift register (LFSR) multiplexers alternately coupled together, where an input of each LFSR flip flop circuit is coupled to an output of an LFSR multiplexer, and where an output of each LFSR flip flop circuit may be provided to an input of an LFSR multiplexer, said linear feedback shift register comprising: a plurality of pre-load flip flop (PLFF) circuits and a plurality of pre-load flip flop (PLFF) multiplexers alternately coupled together, where an input of each PLFF flip flop circuit is coupled to an output of a PLFF multiplexer, and where an output of each PLFF flip flop circuit is coupled to an input of a LFSR multiplexer.
Claim 14
Dependent Claim
142 words
A phase locked loop clock divider circuit comprising a linear feedback shift register of the type comprising a plurality of linear feedback shift register (LFSR) flip flop circuits and a plurality of linear feedback shift register (LFSR) multiplexers alternately coupled together, where an input of each LFSR flip flop circuit is coupled to an output of an LFSR multiplexer, and where an output of each LFSR flip flop circuit may be provided to an input of an LFSR multiplexer, said linear feedback shift register comprising: a plurality of pre-load flip flop (PLFF) circuits and a plurality of pre-load flip flop (PLFF) multiplexers alternately coupled together, where an input of each PLFF flip flop circuit is coupled to an output of a PLFF multiplexer, and where an output of each PLFF flip flop circuit is coupled to an input of a LFSR multiplexer.
Claim 15
Dependent Claim
47 words
A phase locked loop clock divider circuit as claimed in claim 12 wherein said each of said plurality of PLFF multiplexers has a first input coupled to one bit of an input register value and a second input coupled to another bit of said input register value.
Claim 16
Dependent Claim
107 words
A phase locked loop clock divider circuit as claimed in claim 13 having n bits and a polynomial equation of R[m]+R[p] where m is an integer less than n and where p is an integer less than n wherein a PLFF multiplexer that is coupled to a first PLFF flip flop circuit has one input coupled to an input register value bit equal to N[ 0 ] when a load enable signal coupled to said PLFF multiplexer is low and another input coupled to an input register value bit equal to N[m] XNORed with N[p] when said load enable signal coupled to said PLFF multiplexer is high.
Claim 17
Dependent Claim
66 words
A phase locked loop clock divider circuit as claimed in claim 14 comprising a circuit in a feedback path of said linear feedback shift register, wherein said circuit is capable of performing an exclusive NOR function on an output signal of one of said plurality of LFSR flip flop circuits and on an output signal of another one of said plurality of LFSR flip flop circuits.
Claim 18
Dependent Claim
105 words
A phase locked loop clock divider circuit as claimed in claim 13 comprising a linear feedback shift register having six (6) bits and a polynomial equation of R[ 5 ]+R[ 4 ] wherein a PLFF multiplexer that is coupled to a first PLFF flip flop circuit has one input coupled to an input register value bit equal to N[ 0 ] when a load enable signal coupled to said PLFF multiplexer is low and another input coupled to an input register value bit equal to N[ 4 ] XNORed with N[ 5 ] when said load enable signal coupled to said PLFF multiplexer is high.
Claim 19
Dependent Claim
67 words
A phase locked loop clock divider circuit as claimed in claim 16 comprising a circuit in a feedback path of said linear feedback shift register, wherein said circuit is capable of performing an exclusive NOR function on an output signal of an LFSR 4 flip flop circuit and on an output signal of an LFSR 3 flip flop circuit of said plurality of LFSR flip flop circuits.
Claim 20
Dependent Claim
97 words
A phase locked loop clock divider circuit as claimed in claim 17 wherein said circuit in said feedback path comprises: a multiplexer having a first input connected to an output of said LFSR 3 flip flop circuit, and having a second input connected to an inverted version of said output of said LFSR 3 flip flop circuit, and having a load enable input coupled to an output of said LFSR 4 flip flop circuit; and a flip flop circuit having an input coupled to an output of said multiplexer and an output coupled to said feedback path.
Claim 21
Dependent Claim
46 words
A phase locked loop clock divider circuit as claimed in claim 14 wherein each LFSR multiplexer and each PLFF multiplexer has an enable signal input line connected to a load enable circuit that provides a load enable signal that is high for two input clock cycles.
Claim 22
Dependent Claim
65 words
A phase locked loop clock divider circuit as claimed in claim 19 wherein said plurality of pre-load flip flop (PLFF) circuits hold a first linear feedback shift register (LFSR) sequence value when said load enable signal is low; and wherein said plurality of pre-load flip flop (PLFF) circuits hold a second linear feedback shift register (LFSR) sequence value when said load enable signal is high.
Claim 23
Dependent Claim
73 words
A phase locked loop clock divider circuit as claimed in claim 20 capable of operating in a frequency range from approximately six hundred million cycles per second (600 MHz) to approximately nine hundred million cycles per second (900 MHz) where said linear feedback shift register utilizes 0.18 micron process technology and standard flip flop circuits for said pre-load flip flop (PLFF) circuits and for said linear feedback shift register (LFSR) flip flop circuits.
Claim 24
Dependent Claim
78 words
A phase locked loop clock divider circuit as claimed in claim 20 capable of operating in a frequency range from approximately one billion two hundred million cycles per second (1.2 GHz) to approximately one billion five hundred million cycles per second (1.5 GHz) where said linear feedback shift register utilizes 0.18 micron process technology and custom designed flip flop circuits for said pre-load flip flop (PLFF) circuits and for said linear feedback shift register (LFSR) flip flop circuits.
Claim 25
Independent Claim
281 words
A method for providing a linear feedback shift register having n bits where n is an integer, said method comprising the steps of: alternately coupling together a plurality of linear feedback shift register (LFSR) flip flop circuits and a plurality of linear feedback shift register (LFSR) multiplexers, where an input of each LFSR flip flop circuit is coupled to an output of an LFSR multiplexer, and where an output of each LFSR flip flop circuit may be provided to an input of an LFSR multiplexer; alternately coupling together a plurality of pre-load flip flop (PLFF) circuits and a plurality of pre-load flip flop (PLFF) multiplexers, where an input of each PLFF flip flop circuit is coupled to an output of a PLFF multiplexer, and where an output of each PLFF flip flop circuit is coupled to an input of an LFSR multiplexer; coupling an input register value bit to a first input of each of said plurality of PLFF multiplexers; coupling an input register value bit to a second input of each of said plurality of PLFF multiplexers; coupling to one input of a PLFF multiplexer that is coupled to a first PLFF flip flop circuit an input register value bit that is equal to N[ 0 ] when a load enable signal coupled to said PLFF multiplexer is low; coupling to another input of said PLFF multiplexer that is coupled to said first PLFF flip flop circuit an input register value bit that is equal to N[m] XNORed with N[p] where said linear feedback shift register (LFSR) has a polynomial equation of R[m]+R[p] where m is an integer less than n and where p is an integer less than n.
Claim 26
Independent Claim
281 words
A method for providing a linear feedback shift register having n bits where n is an integer, said method comprising the steps of: alternately coupling together a plurality of linear feedback shift register (LFSR) flip flop circuits and a plurality of linear feedback shift register (LFSR) multiplexers, where an input of each LFSR flip flop circuit is coupled to an output of an LFSR multiplexer, and where an output of each LFSR flip flop circuit may be provided to an input of an LFSR multiplexer; alternately coupling together a plurality of pre-load flip flop (PLFF) circuits and a plurality of pre-load flip flop (PLFF) multiplexers, where an input of each PLFF flip flop circuit is coupled to an output of a PLFF multiplexer, and where an output of each PLFF flip flop circuit is coupled to an input of an LFSR multiplexer; coupling an input register value bit to a first input of each of said plurality of PLFF multiplexers; coupling an input register value bit to a second input of each of said plurality of PLFF multiplexers; coupling to one input of a PLFF multiplexer that is coupled to a first PLFF flip flop circuit an input register value bit that is equal to N[ 0 ] when a load enable signal coupled to said PLFF multiplexer is low; coupling to another input of said PLFF multiplexer that is coupled to said first PLFF flip flop circuit an input register value bit that is equal to N[m] XNORed with N[p] where said linear feedback shift register (LFSR) has a polynomial equation of R[m]+R[p] where m is an integer less than n and where p is an integer less than n.
Claim 27
Dependent Claim
60 words
A method as claimed in claim 23 further comprising the step of: coupling to an input of an LFSR multiplexer a feedback signal generated by performing an exclusive NOR function on an output signal of one of said plurality of LFSR flip flop circuits and on an output signal of another one of said plurality of LFSR flip flop circuits.
Claim 28
Dependent Claim
30 words
A method as claimed in claim 24 where the value of n is six (6) and the value of m is five (5) and the value of p is (4).
Claim 29
Dependent Claim
112 words
A method as claimed in claim 25 wherein said step of coupling to an input of an LFSR multiplexer a feedback signal generated by performing an exclusive NOR function on an output signal of one of said plurality of LFSR flip flop circuits and on an output signal of another one of said plurality of LFSR flip flop circuits comprises the step of: coupling to an input of an LFSR multiplexer a feedback signal generated by performing an exclusive NOR function on an output signal of an LFSR 4 flip flop circuit and on an output signal of an LFSR 3 flip flop circuit of said plurality of LFSR flip flop circuits.
Claim 30
Dependent Claim
99 words
A method as claimed in claim 24 further comprising the steps of: coupling to an enable signal input line of each LFSR multiplexer and to an enable signal input line of each PLFF multiplexer a load enable signal that is high for two input clock cycles; holding in said plurality of pre-load flip flop (PLFF) circuits a first linear feedback shift register (LFSR) sequence value when said load enable signal is low; and holding in said plurality of pre-load flip flop (PLFF) circuits a second linear feedback shift register (LFSR) sequence value when said load enable signal is high.
Claim 31
Dependent Claim
75 words
A method as claimed in claim 27 comprising the steps of: fabricating said linear feedback shift register with 0.18 micron technology; providing standard flip flop circuits for said pre-load flip flop (PLFF) circuits and for said linear feedback shift register (LFSR) flip flop circuits; and operating said linear feedback shift register within a frequency range from approximately six hundred million cycles per second (600 MHz) to approximately nine hundred million cycles per second (900 MHz).
Claim 32
Dependent Claim
80 words
A method as claimed in claim 27 comprising the steps of: fabricating said linear feedback shift register with 0.18 micron technology; providing custom designed flip flop circuits for said pre-load flip flop (PLFF) circuits and for said linear feedback shift register (LFSR) flip flop circuits; and operating said linear feedback shift register within a frequency range from approximately one billion two hundred million cycles per second (1.2 GHz) to approximately one billion five hundred million cycles per second (1.5 GHz).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-22 | 2006-01-21 | 2006-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-22 | 2010-01-21 | 2010-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-22 | 2014-01-21 | 2014-07-23 | $7700.00 | Window Closed / Lapsed |