Multifunction register

Claim 2

A multifunction data storage register, comprising: at least one first register cell having, a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input logic circuit having a first input connected to said first output signal of said first input multiplexer and a second input connected to a cell output signal and having a third output signal, a first shift register latch having an input connected to said third output signal of said first input logic circuit and having a fourth output signal, a first output logic circuit having a first input connected to said fourth output signal of said first shift register latch and a second input connected to a feedback signal and having a fifth output signal, and a first output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a first cell output signal, and at least one second register cell having, a second input multiplexer for selecting between two input signals responsive to said one or more control signals and having a seventh output signal, a second input logic circuit having a first input connected to said seventh output signal of said second input multiplexer and a second input connected to a cell output signal and having an eighth output signal, and a second shift register latch having an input connected to said eighth output signal of said second input logic circuit and having a second cell output signal.

Claim 3

The register of claim 1, wherein said at least one first register cell is three such cells and said at least one second register cell is thirteen such cells.

Claim 4

The register of claim 2, wherein said first register cells form bit positions zero, two and fifteen and said second register cells form the remaining bit positions.

Claim 5

The register of claim 3, wherein said output signals from said first and second input logic circuits are provided to a plurality of summing logic circuits.

Claim 6

The register of claim 3, wherein the output signal from said first shift register latch corresponding to bit position fifteen also provides said feedback signal.

Claim 7

The register of claim 1, wherein one of said two inputs to said input multiplexers is data from a data bus.

Claim 8

The register of claim 1, wherein one of said two inputs to said input multiplexers is inverted data addresses from a data address bus.

Claim 9

The register of claim 1, wherein said one or more control signals shift the register function between a parallel signature analysis mode and a breakpoint mode.

Claim 10

A multifunction register, comprising: a first register cell having, a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input exclusive not OR circuit having a first input connected to said first output signal and a second input connected to a second output signal and having a third output signal, a first shift register latch having an input connected to said third output signal and having a fourth output signal, a first output exclusive not OR circuit having a first input connected to said fourth output signal and a second input connected to a feedback signal and having a fifth output signal, and a first output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a sixth output signal, a second register cell having, a second input multiplexer for selecting between two input signals responsive to said one or more control signals and having a seventh output signal, a second input exclusive not OR circuit having a first input connected to said seventh output signal and a second input connected to a sixth output signal and having an eighth output signal, and a second shift register latch having an input connected to said eighth output signal and having a ninth output signal, a third register cell having, a third input multiplexer for selecting between two input signals responsive to one or more control signals and having a tenth output signal, a third input exclusive not OR circuit having a first input connected to said tenth output signal and a second input connected to said ninth output signal and having a eleventh output signal, a third shift regsiter latch having an input connected to said eleventh output signal and having a twelvfth output, a third output exclusive not OR circuit having a first input connected to said twelfth output signal and a second input connected to a feedback signal and having a thirteenth output signal, and a third out multiplexer for selecting between said twelfth output signal and said thirteenth output signal responsive to said one or more control signals and having a fourteenth output signal, a fourth register cell having, a fourth input multiplexer for selecting between two input signals responsive to said one or more control signals and having a fifteenth output signal, a fourth input exclusive not OR circuit having a first input connected to said fifteenth output signal and a second input connected to said fourteenth output signal and having an sixteenth output signal, and a fourth shift register latch having an input connected to said sixteenth output signal and having a second output signal.

Claim 11

A multifunction register, comprising: a first register cell having, a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input exclusive not OR circuit having a first input connected to said first output signal and a second input connected to a second output signal and having a third output signal, a first shift register latch having an input connected to said third output signal and having a fourth output signal, a first output exclusive not OR circuit having a first input connected to said fourth output signal and a second input connected to a feedback signal and having a fifth output signal, and a first output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a sixth output signal, a second register cell having, a second input multiplexer for selecting between two input signals responsive to said one or more control signals and having a seventh output signal, a second input exclusive not OR circuit having a first input connected to said seventh output signal and a second input connected to a sixth output signal and having an eighth output signal, and a second shift register latch having an input connected to said eighth output signal and having a ninth output signal, a third register cell having, a third input multiplexer for selecting between two input signals responsive to one or more control signals and having a tenth output signal, a third input exclusive not OR circuit having a first input connected to said tenth output signal and a second input connected to said ninth output signal and having a eleventh output signal, a third shift regsiter latch having an input connected to said eleventh output signal and having a twelvfth output, a third output exclusive not OR circuit having a first input connected to said twelfth output signal and a second input connected to a feedback signal and having a thirteenth output signal, and a third out multiplexer for selecting between said twelfth output signal and said thirteenth output signal responsive to said one or more control signals and having a fourteenth output signal, a fourth register cell having, a fourth input multiplexer for selecting between two input signals responsive to said one or more control signals and having a fifteenth output signal, a fourth input exclusive not OR circuit having a first input connected to said fifteenth output signal and a second input connected to said fourteenth output signal and having an sixteenth output signal, and a fourth shift register latch having an input connected to said sixteenth output signal and having a second output signal.

Claim 12

A register cell for a multifunctional register, comprising: an input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, an input exclusive not OR circuit having a first input connected to said first output signal and a second input connected to a cell output signal and having a third output signal, a shift register latch having an input connected to said third output signal and having a fourth output signal, an output exclusive not OR circuit having a first input connected to said fourth output signal and a second input connected to a feedback signal and having a fifth output signal, and an output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a cell out signal.

Claim 13

A register cell for a multifunctional register, comprising: an input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, an input exclusive not OR circuit having a first input connected to said first output signal and a second input connected to a cell output signal and having a third output signal, a shift register latch having an input connected to said third output signal and having a fourth output signal, an output exclusive not OR circuit having a first input connected to said fourth output signal and a second input connected to a feedback signal and having a fifth output signal, and an output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a cell out signal.

Claim 14

A register cell for a multifunctional register, comprising: an input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, an input exclusive not OR circuit having a first input connected to said first output signal and a second input connected to a cell output signal and having a second output signal, and a shift register latch having an input connected to said second output signal and having a cell output signal.

Claim 15

A register cell for a multifunctional register, comprising: an input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, an input exclusive not OR circuit having a first input connected to said first output signal and a second input connected to a cell output signal and having a second output signal, and a shift register latch having an input connected to said second output signal and having a cell output signal.