US6791877B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with non-volatile memory and random access memory
Assignee: Renesas Electronics Corp
•
Filing: 2002-06-10
•
Granted: 2004-09-14
•
Expires: 2022-06-10
Abstract
Abstract A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.
Inventors
- 👤 Seiji Miura
- 👤 Kazushige Ayukawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:27
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; G11C5/00; G11C5/02; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0238; G06F12/0246; G11C11/00; G11C11/005; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40603; G11C11/40607; G11C11/41; G11C11/412; G11C16/06; G11C16/10; G11C16/26; G11C16/32; G11C29/00; G11C29/70; G11C5/025; G11C5/04
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
75 words
A semiconductor device, comprising: a non-volatile memory having a first reading time; a random access memory having a second reading time which is more than 100 times shorter than said first reading time; a circuit that includes a control circuit connected to both said non-volatile memory and said random access memory and used to control access to said random access memory and said non-volatile memory; and a plurality of input/output terminals connected to said circuit.
Claim 2
Dependent Claim
75 words
A semiconductor device, comprising: a non-volatile memory having a first reading time; a random access memory having a second reading time which is more than 100 times shorter than said first reading time; a circuit that includes a control circuit connected to both said non-volatile memory and said random access memory and used to control access to said random access memory and said non-volatile memory; and a plurality of input/output terminals connected to said circuit.
Claim 3
Dependent Claim
29 words
The semiconductor device according to claim 1 , wherein said non-volatile memory is connected to a plurality of said input/output terminals and is accessed via said random access memory.
Claim 4
Dependent Claim
35 words
The semiconductor device according to claim 1 , wherein part of data stored in said non-volatile memory is transferred to a first area of said random access memory just after said semiconductor device is powered.
Claim 5
Dependent Claim
33 words
The semiconductor device according to claim 3 , wherein accesses to said non-volatile memory are actually directed to said first area of said random access memory via a plurality of said input/output terminals.
Claim 6
Dependent Claim
58 words
The semiconductor device according to claim 4 , wherein said control circuit includes a circuit that stores an address in which data is written due to an external access to said first area of said random access memory, and further wherein said data written to said first area is rewritten to said non-volatile memory at a predetermined timing.
Claim 7
Dependent Claim
61 words
The semiconductor device according to claim 1 , wherein said random access memory includes a first area in which part of data stored in said non-volatile memory and transferred therefrom is copied so as to be used as a buffer area of an access to said non-volatile memory; and a second area to be used as a work area from external.
Claim 8
Dependent Claim
52 words
The semiconductor device according to claim 1 , wherein said random access memory is a DRAM synchronized with a clock and wherein an interface of this DRAM synchronized with a clock is used to access said non-volatile memory and said random access memory from external via a plurality of said input/output terminals.
Claim 9
Dependent Claim
29 words
The semiconductor device according to claim 1 , wherein said non-volatile memory is a NAND flash memory and said random access memory is a DRAM synchronized with a clock.
Claim 10
Dependent Claim
58 words
The semiconductor device according to claim 1 , wherein said semiconductor device is a multi-chip memory module that includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip; and said first semiconductor chip includes said non-volatile memory, said second semiconductor chip includes said circuit, and said third semiconductor chip includes said random access memory.
Claim 11
Dependent Claim
45 words
The semiconductor device according to claim 1 , wherein said circuit includes a static random access memory; and an interface of said static random access memory is used to access said non-volatile memory and said random access memory via a plurality of said input/output terminals.
Claim 12
Dependent Claim
46 words
The semiconductor device according to claim 1 , wherein said random access memory is a dynamic random access memory; and refreshment of said dynamic random access memory is hidden from external while said dynamic random access memory is accessed via a plurality of said input/output terminals.
Claim 13
Dependent Claim
81 words
The semiconductor device according to claim 1 ; wherein said semiconductor device is a multi-chip module in which a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip are mounted and molded on a substrate; and said first semiconductor chip includes said non-volatile memory, said second semiconductor chip includes said circuit, said third semiconductor chip includes part of said random access memory, and said fourth semiconductor chip includes part of said random access memory.
Claim 14
Dependent Claim
61 words
A semiconductor device, comprising: a flash memory; a DRAM; a control circuit connected to both said flash memory and said DRAM and enabled to control access to said DRAM and said flash memory; and a plurality of input/output terminals connected to said circuit, wherein accesses to said flash memory via a plurality of said input/output terminals are made via said DRAM.
Claim 15
Dependent Claim
61 words
A semiconductor device, comprising: a flash memory; a DRAM; a control circuit connected to both said flash memory and said DRAM and enabled to control access to said DRAM and said flash memory; and a plurality of input/output terminals connected to said circuit, wherein accesses to said flash memory via a plurality of said input/output terminals are made via said DRAM.
Claim 16
Dependent Claim
38 words
The semiconductor device according to claim 13 , wherein part of data stored in said flash memory is transferred to a first area of said DRAM and stored there just after said semiconductor device is powered from external.
Claim 17
Dependent Claim
54 words
The semiconductor device according to claim 14 , wherein said control circuit includes a circuit that stores an address in which data is written due to an access to said first area from external; and further wherein said data written in said first area is written into said non-volatile memory at a predetermined timing.
Claim 18
Dependent Claim
57 words
A semiconductor device, comprising: a non-volatile memory that includes a first area and a second area; a random access memory that includes a third area and a fourth area; and a memory controller connected to both said non-volatile memory and said random access memory, wherein the same data is held in said first and said third areas.
Claim 19
Dependent Claim
57 words
A semiconductor device, comprising: a non-volatile memory that includes a first area and a second area; a random access memory that includes a third area and a fourth area; and a memory controller connected to both said non-volatile memory and said random access memory, wherein the same data is held in said first and said third areas.
Claim 20
Dependent Claim
63 words
The semiconductor device according to claim 16 , wherein said memory controller includes an error correction circuit that detects and corrects errors of data read from said non-volatile memory, wherein data corrected by said error correction circuit is transferred to said third area during data transfer to said third area of said random access memory from said first area of said non-volatile memory.
Claim 21
Dependent Claim
68 words
The semiconductor device according to claim 16 , wherein said memory controller stores an address of said third area, in which data is updated and transfers said updated data corresponding to said address to a first area from said third area when the power supply to said semiconductor device is shut off and shuts off said power supply to said random access memory after said transfer is ended.
Claim 22
Dependent Claim
70 words
The semiconductor device according to claim 16 , wherein said memory controller includes an access priority decision circuit and defines a refreshing request issued to said random access memory as a first priority, a request of an access to said random access memory from external as a second priority, and an access request related to data transfer between said non-volatile memory and said random access memory as a third priority.
Claim 23
Dependent Claim
142 words
The semiconductor device according to claim 16 , wherein said memory controller is formed on said first semiconductor chip, said random access memory is formed on said second semiconductor chip, and said non-volatile memory is formed on said third semiconductor chip; said semiconductor device also includes a molded device in which said first, second, and third semiconductor chips are included; and said molded device includes a plurality of first electrodes for connecting said first and second semiconductor chips to each other electrically, a plurality of second electrodes for connecting said first and third semiconductor chips to each other electrically, a plurality of third electrodes for connecting said first semiconductor chip to an external device located outside said molded device electrically, and a plurality of fourth electrodes for connecting said third semiconductor chip to an external device located outside said molded device electrically.
References Cited (Backward Citations)
EP0566306A2
Cited
JPH07146820A
Cited
US5530673A
Cited
US5650976A
Cited
US6029046A
Cited
US6484270B1
Cited
US6324103B2
Cited
JP2001005723A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-09-14 | 2008-03-15 | 2008-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-09-14 | 2012-03-15 | 2012-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-09-14 | 2016-03-15 | 2016-09-14 | $7700.00 | Window Closed / Lapsed |