EP0566306A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1993-04-06
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Granted: —
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Expires: 2013-04-06
Abstract
Abstract A semiconductor memory device constructed by packaging a nonvolatile memory chip capable of being electrically written and erased and a RAM into a common package.
Inventors
- 👤 Masamichi Ishihara
- 👤 Hiroshi Satou
- 👤 Hiroaki Kotani
- 👤 Keiichi Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 21:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/005; G11C14/00; G06; G06F; G06F2212/00; G06F2212/20; G06F2212/205; G06F3/00; G06F3/06; G06F3/0601; G06F3/0668; G06F3/0671; G06F3/0683; G06F3/0685; H; H10; H10W; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/853; H10W72/865; H10W74/00; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
88 words
A semiconductor memory device to be packaged in one package, comprising: a volatile memory formed on one semiconductor substrate and including a plurality of first memory cells, wherein each of said first memory cells has one MOSFET and one capacitor; and a nonvolatile memory formed on one semiconductor substrate and including a plurality of second memory cells, wherein each of said second memory cells has a source, a drain, and a floating gate and a control gate over a channel region formed between said source and said drain.
Claim 2
Dependent Claim
88 words
A semiconductor memory device to be packaged in one package, comprising: a volatile memory formed on one semiconductor substrate and including a plurality of first memory cells, wherein each of said first memory cells has one MOSFET and one capacitor; and a nonvolatile memory formed on one semiconductor substrate and including a plurality of second memory cells, wherein each of said second memory cells has a source, a drain, and a floating gate and a control gate over a channel region formed between said source and said drain.
Claim 3
Dependent Claim
25 words
A semiconductor memory device according to claim 1, wherein each of said volatile memory and said nonvolatile memory has an equal number of memory cells.
Claim 4
Dependent Claim
60 words
A semiconductor memory device according to claim 2, wherein each of said volatile memory and said nonvolatile memory is fed with a mode selecting signal so that. said volatile memory is accessed when said mode selecting signal is at a first level and so that said nonvolatile memory is accessed when said mode selecting signal is at a second level.
Claim 5
Dependent Claim
42 words
A semiconductor memory device according to claim 3, wherein the data read out from said volatile memory when said mode selecting signal takes said first level are stored in said nonvolatile memory by setting said mode selecting signal to said second level.
Claim 6
Dependent Claim
42 words
A semiconductor memory device according to claim 3, wherein the data read out from said nonvolatile memory when said mode selecting signal takes said second level are stored in said nonvolatile memory by setting said mode selecting signal to said first level.
Claim 7
Dependent Claim
35 words
A semiconductor memory device according to claim 4, wherein each of said volatile memory and said nonvolatile memory further includes a plurality of address terminals coupled to a plurality of address terminals of said package.
Claim 8
Dependent Claim
35 words
A semiconductor memory device according to claim 5, wherein each of said volatile memory and said nonvolatile memory further includes a plurality of address terminals coupled to a plurality of address terminals of said package.
Claim 9
Dependent Claim
29 words
A semiconductor memory device according to claim 2, wherein said volatile memory further includes a plurality of address terminals coupled to a plurality of address terminals of said package.
Claim 10
Dependent Claim
80 words
A semiconductor memory device according to claim 8, wherein each of said volatile memory and said nonvolatile memory is fed with a transfer direction instructing signal so that a data transfer is executed between said volatile memory and outside of said package when said transfer direction instructing signal is at a first level and so that a data transfer is executed between said volatile memory and said nonvolatile memory when said transfer direction instructing signal is at a second level.
Claim 11
Dependent Claim
46 words
A semiconductor memory device according to claim 9, wherein said nonvolatile memory further includes first control means for feeding a first control signal to said volatile memory, and wherein volatile memory further includes second control means for feeding a second control signal to said nonvolatile memory.
Claim 12
Dependent Claim
62 words
A semiconductor memory device according to claim 10, wherein data stored in said nonvolatile memory are read, if fed with said second control signal, when said transfer direction indicating signal is at said second level, and wherein said volatile memory stores said read-out data if fed with said first control signal when said transfer direction indicating signal is at said second level.
Claim 13
Dependent Claim
62 words
A semiconductor memory device according to claim 10, wherein data stored in said volatile memory are read, if fed with said first control signal, when said transfer direction indicating signal is at said second level, and wherein said nonvolatile memory stored said read-out data if fed with said second control signal when said transfer direction indicating signal is at said second level.
Claim 14
Dependent Claim
96 words
A microcomputer system comprising a CPU, and a memory device to be packaged in one package, said memory device comprising: a volatile memory formed on one semiconductor substrate and including a plurality of first memory cells, wherein each of said first memory cells has one MOSFET and one capacitor; and a nonvolatile memory formed on one semiconductor substrate and including a plurality of second memory cells, wherein each of said second memory cells has a source, a drain, and a floating gate and a control gate over channel region formed between said source and said drain.
Claim 15
Dependent Claim
96 words
A microcomputer system comprising a CPU, and a memory device to be packaged in one package, said memory device comprising: a volatile memory formed on one semiconductor substrate and including a plurality of first memory cells, wherein each of said first memory cells has one MOSFET and one capacitor; and a nonvolatile memory formed on one semiconductor substrate and including a plurality of second memory cells, wherein each of said second memory cells has a source, a drain, and a floating gate and a control gate over channel region formed between said source and said drain.
Claim 16
Dependent Claim
25 words
A microcomputer system according to claim 13, further comprising control means for producing a mode selecting signal based on a control signal from said CPU.
Claim 17
Dependent Claim
24 words
A microcomputer system according to claim 14, wherein each of said volatile memory and said nonvolatile memory has an equal number of memory cells.
Claim 18
Dependent Claim
59 words
A microcomputer system according to claim 15, wherein each of said volatile memory and said nonvolatile memory is fed with a mode selecting signal so that said volatile memory is accessed when said mode selecting signal is at a first level and so that said nonvolatile memory is accessed when said mode selecting signal is at a second level.
Claim 19
Dependent Claim
47 words
A microcomputer system according to claim 16, wherein the data stored in said nonvolatile memory are read when said mode selecting signal takes said first level and wherein said read out data are stored in said volatile memory when said mode selecting signal takes said second level.
Claim 20
Dependent Claim
41 words
A microcomputer system according to claim 16, wherein the data read out from said volatile memory when said mode selecting signal takes said second level are stored in said nonvolatile memory by setting said mode selecting signal to said first level.
Claim 21
Dependent Claim
34 words
A microcomputer system according to claim 17, wherein each of said volatile memory and said nonvolatile memory further includes a plurality of address terminals coupled to a plurality of address terminals of said package.
Claim 22
Dependent Claim
34 words
A microcomputer system according to claim 18, wherein each of said volatile memory and said nonvolatile memory further includes a plurality of address terminals coupled to a plurality of address terminals of said package.
Claim 23
Dependent Claim
28 words
A microcomputer system according to claim 15, wherein said volatile memory further includes a plurality of address terminals coupled to a plurality of address terminals of said package.
Claim 24
Dependent Claim
79 words
A microcomputer system according to claim 21, wherein each of said volatile memory and said nonvolatile memory is fed with a transfer direction instructing signal so that a data transfer is executed between said volatile memory and outside of said package when said transfer direction instructing signal is at a first level and so that a data transfer is executed between said volatile memory and said nonvolatile memory when said transfer direction instructing signal is at a second level.
Claim 25
Dependent Claim
45 words
A microcomputer system according to claim 22, wherein said nonvolatile memory further includes first control means for feeding a first control signal to said volatile memory, and wherein volatile memory further includes second control means for feeding a second control signal to said nonvolatile memory.
Claim 26
Dependent Claim
61 words
A microcomputer system according to claim 23, wherein data stored in said nonvolatile memory are read, if fed with said second control signal, when said transfer direction indicating signal is at said second level, and wherein said volatile memory stores said read-out data if fed with said first control signal when said transfer direction indicating signal is at said second level.
Claim 27
Dependent Claim
61 words
A microcomputer system according to claim 23, wherein data stored in said nonvolatile memory are read, if fed with said first control signal, when said transfer direction indicating signal is at said second level, and wherein said nonvolatile memory stored said read-out data if fed with said second control signal when said transfer direction indicating signal is at said second level.
References Cited (Backward Citations)
No citation records indexed.
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