Dual strobed negative pumped wordlines for dynamic random access memories

Claim 2

A memory circuit, comprising: a) a first node adapted to alternately receiving a first potential and a second potential; b) a second node adapted to receive a third potential; c) a wordline electrically coupleable to one of said first node and said second node; and d) a driver circuit electrically interposed between said first node and said second node and in electrical communication with said wordline, said driver circuit adapted to electrically couple said wordline to said first node and to drive a potential of said wordline toward the first potential, and adapted to electrically couple said wordline to said first node and to drive the potential of said wordline toward the second potential, and adapted to electrically decouple said wordline from said first node and to electrically couple said wordline to said second node and to drive the potential of the wordline toward the third potential, wherein said first and said second and said third potentials are different one from the other.

Claim 3

The memory circuit as specified in claim 1, further comprising a decode circuit for supplying the first and the second potentials to said first node.

Claim 4

The memory circuit as specified in claim 1, wherein a value of the second potential is within a range of potentials lying between a value of the first potential and a value of the third potential.

Claim 5

A memory circuit, comprising: a) memory cells for storing data; b) a wordline in electrical association with said memory cells, wherein the wordline is activated when one of the memory cells is addressed and wherein the wordline is deactivated subsequent to being activated; c) a primary decode circuit for supplying a primary decode signal having an active state and an inactive state; d) a secondary decode circuit for supplying a first secondary decode signal and a second secondary decode signal; and e) a driver circuit adapted to drive a potential of the wordline toward a value of a potential of the first secondary decode signal in response to the active state of the primary decode signal, and adapted to drive the potential of the wordline toward a value of a potential of the second secondary decode signal in response to the active state of the primary decode signal, and adapted to drive the potential of the deactivated wordline toward a supply potential.

Claim 6

A memory circuit, comprising: a) memory cells for storing data; b) a wordline in electrical association with said memory cells, wherein the wordline is activated when one of the memory cells is addressed and wherein the wordline is deactivated subsequent to being activated; c) a primary decode circuit for supplying a primary decode signal having an active state and an inactive state; d) a secondary decode circuit for supplying a first secondary decode signal and a second secondary decode signal; and e) a driver circuit adapted to drive a potential of the wordline toward a value of a potential of the first secondary decode signal in response to the active state of the primary decode signal, and adapted to drive the potential of the wordline toward a value of a potential of the second secondary decode signal in response to the active state of the primary decode signal, and adapted to drive the potential of the deactivated wordline toward a supply potential.

Claim 7

The memory circuit as specified in claim 4, wherein the potential of the wordline is driven to the supply potential in response to the inactive state of the primary decode signal.

Claim 8

The memory circuit as specified in claim 4, further comprising a delay circuit for delaying a transition of the second secondary decode signal to create a delayed second secondary decode signal, wherein the potential of the wordline is driven to the supply potential in response to the delayed second secondary decode signal.

Claim 9

The memory circuit as specified in claim 4, wherein the value of the potential of the second secondary decode signal is between the value of the potential of first secondary decode signal and a value of the supply potential.

Claim 10

A memory circuit, comprising: a) a first node adapted to alternately accept a reference potential and a first potential greater than the reference potential; b) a second node adapted to accept a second potential less than the reference potential; c) a wordline electrically coupleable to one of said first node and said second node; and d) a driver circuit electrically interposed between said first node and said second node and in electrical communication with said wordline, said driver circuit adapted to electrically couple said wordline to said first node and to drive a potential of said wordline toward the first potential when said wordline is activated, and adapted to electrically couple said wordline to said first node and to drive the potential of said wordline toward the reference potential at an initial deactivation of the wordline, and adapted to electrically decouple said wordline from said first node and to electrically couple said wordline to said second node and to drive the potential of the wordline toward the second potential during a reset cycle subsequent to the initial deactivation of the wordline.

Claim 11

A memory circuit, comprising: a) a first node adapted to alternately accept a reference potential and a first potential greater than the reference potential; b) a second node adapted to accept a second potential less than the reference potential; c) a wordline electrically coupleable to one of said first node and said second node; and d) a driver circuit electrically interposed between said first node and said second node and in electrical communication with said wordline, said driver circuit adapted to electrically couple said wordline to said first node and to drive a potential of said wordline toward the first potential when said wordline is activated, and adapted to electrically couple said wordline to said first node and to drive the potential of said wordline toward the reference potential at an initial deactivation of the wordline, and adapted to electrically decouple said wordline from said first node and to electrically couple said wordline to said second node and to drive the potential of the wordline toward the second potential during a reset cycle subsequent to the initial deactivation of the wordline.

Claim 12

The memory circuit as specified in claim 8, further comprising a secondary decode circuit adapted to supply the first potential and the reference potential at said first node.

Claim 13

The memory circuit as specified in claim 9, wherein said secondary decode circuit generates a delayed complementary signal which is an input signal of said driver circuit.

Claim 14

The memory circuit as specified in claim 9, wherein the secondary decode circuit is responsive to a row address strobe (RAS) signal and an address signal such that when an address selects said wordline and the RAS signal is active, the secondary decode circuit supplies the first potential at said first node, and such that when the RAS signal is inactive, the secondary decode circuit supplies the reference potential at said first node.

Claim 15

The memory circuit as specified in claim 8, further comprising a primary decode circuit for controlling said driver circuit during electrical coupling and electrical decoupling of said wordline to said first and said second nodes.

Claim 16

The memory circuit as specified in claim 8, further comprising: a) primary decode circuit for controlling said driver circuit during electrical coupling and electrical decoupling of said wordline to said first and said second nodes; and b) a secondary decode circuit adapted to supply the first potential and the reference potential at said first node and adapted to generate a complementary signal, having a logic state after a time delay which is complementary to a potential supplied at said first node, said complementary signal being an input of said driver circuit.

Claim 17

The memory circuit as specified in claim 13, wherein the driver circuit comprises a first driver portion and a second driver portion, wherein said first driver portion is responsive to said primary decode circuit and said secondary decode circuit, and wherein said second driver portion is responsive to said secondary decode circuit.

Claim 18

The memory circuit as specified in claim 14, wherein said secondary decode circuit maintains an activation of said second driver portion to maintain an electrical coupling of said wordline to said second node when said wordline is non-selected.