US6324103B2
Expired / Lapsed
US
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Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
Assignee: Renesas Electronics Corp
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Filing: 2001-01-09
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Granted: 2001-11-27
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Expires: 2021-01-09
Abstract
Abstract To improve the efficiency for repairing a defect of a large-scale integrated circuit. A semiconductor integrated circuit device comprises, a central processing unit ( 10 ), an electrically reprogrammable nonvolatile memory ( 11 ) and a volatile memory ( 12, 13 ) while sharing a dat bus ( 16 ), and utilizes the stored information of the nonvolatile memory so as to repair a defect of the volatile memory. This volatile memory includes volatile storage circuit ( 12 AR, 13 AR) for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory. Any fuse program circuit is not needed for the detect repair, but a defect to occur after a burn-in can be newly repaired so that the new defect can be repaired even after the packaging over a circuit substrate.
Inventors
- 👤 Mitsuru Hiraki
- 👤 Shoji Shukuri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:01
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/08; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40615; G11C11/4063; G11C11/407; G11C11/4072; G11C11/4074; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C29/00; G11C29/02; G11C29/021; G11C29/026; G11C29/028; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C29/4401; G11C29/50; G11C29/50012; G11C7/20; G11C7/22; G11C16/10; G11C16/20; G11C2029/0401; G11C2029/1208; G11C29/70
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
181 words
A semiconductor integrated circuit device comprising, over one semiconductor substrate while sharing a data bus: a central processing unit; a nonvolatile memory which may be electrically reprogrammed and accessed by said central processing unit; and a volatile memory which may be accessed by said central processing unit, wherein said nonvolatile memory and said volatile memory individually include register means having data input terminals connected with said data bus, so that their functions are partially determined according to the information set in said register means, wherein said nonvolatile memory includes as plurality of nonvolatile memory cells, some of which are nonvolatile memory cells for storing initialization data, and has an operation mode for allowing the initialization data storing nonvolatile memory cells to be reprogrammed, and an operation mode for inhibiting the same, so that initialization data is read out from the nonvolatile memory cells and outputted in response to an instruction to initialize said semiconductor integrated circuit device, and wherein said register means latches initialization data from said nonvolatile memory in response to the instruction to initialize said semiconductor integrated circuit device.
Claim 2
Dependent Claim
181 words
A semiconductor integrated circuit device comprising, over one semiconductor substrate while sharing a data bus: a central processing unit; a nonvolatile memory which may be electrically reprogrammed and accessed by said central processing unit; and a volatile memory which may be accessed by said central processing unit, wherein said nonvolatile memory and said volatile memory individually include register means having data input terminals connected with said data bus, so that their functions are partially determined according to the information set in said register means, wherein said nonvolatile memory includes as plurality of nonvolatile memory cells, some of which are nonvolatile memory cells for storing initialization data, and has an operation mode for allowing the initialization data storing nonvolatile memory cells to be reprogrammed, and an operation mode for inhibiting the same, so that initialization data is read out from the nonvolatile memory cells and outputted in response to an instruction to initialize said semiconductor integrated circuit device, and wherein said register means latches initialization data from said nonvolatile memory in response to the instruction to initialize said semiconductor integrated circuit device.
Claim 3
Dependent Claim
151 words
A semiconductor integrated circuit device according to claim 1 , further comprising a clock control circuit adapted to be initialized in response to a first state of a reset signal for indicating initialization of the semiconductor integrated circuit, wherein said clock control circuit outputs a first timing signal having a plurality of phases, shifted in activation timing from one another, in response to a change of said reset signal from the first state to a second state, and then outputs a second timing signal for causing said central processing unit to start a reset exceptional operation, wherein said nonvolatile memory reads out and outputs said initialization data consecutively in a plurality of cycles from the nonvolatile memory cells in response to the activation timing of said first timing signal, and wherein said register means latches the data bus consecutively for individual reading cycles of said initialization data from the nonvolatile memory.
Claim 4
Dependent Claim
39 words
A semiconductor integrated circuit device according to claim 1 , wherein said volatile memory utilizes information latched by corresponding register means, as repair information for repairing defective normal volatile memory cells by replacing them with redundancy volatile memory cells.
Claim 5
Dependent Claim
39 words
A semiconductor integrated circuit device according to claim 1 , wherein said nonvolatile memory utilizes information latched by corresponding register means, as repair information for repairing defective normal nonvolatile memory cells by replacing them with redundancy nonvolatile memory cells.
Claim 6
Dependent Claim
51 words
A semiconductor integrated circuit device according to claim 1 , wherein said volatile memory includes dynamic memory cells as the volatile memory cells so that information latched by said register means corresponding to said volatile memory is utilized as control information for specifying a refresh interval of said dynamic memory cells.
Claim 7
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 1 , wherein said volatile memory utilizes information latched by corresponding register means, as control information for specifying the timing of an internal control signal.
Claim 8
Dependent Claim
84 words
A semiconductor integrated circuit device according to claim 1 , further comprising an internal voltage generation circuit for generating an internal power voltage by inputting the power voltage of an external power supply, wherein said internal voltage generation circuit includes latch means for latching control information for determining a reference voltage for specifying the level of the internal power voltage, wherein said latch means latches a portion of the initialization data to be read out from said nonvolatile storage unit, as the control information.
Claim 9
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 1 , wherein said nonvolatile memory is a flash memory, and wherein some of the nonvolatile memory cells store a program to be executed by said central processing unit.
Claim 10
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 1 , wherein said volatile memory is a DRAM and work memory of said central processing unit.
Claim 11
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 1 , wherein said volatile memory is a fast accessing memory including a SRAM.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-26 | 2005-05-28 | 2005-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-26 | 2009-05-28 | 2009-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-26 | 2013-05-28 | 2013-11-27 | $7700.00 | Window Closed / Lapsed |