US5694359A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flash memory device
Assignee: SK Hynix Inc
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Filing: 1996-12-27
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Granted: 1997-12-02
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Expires: 2016-12-27
Abstract
Abstract The present invention relates to a flash memory cell device having a repair circuit for replacing a fail cell of main memory cell arrays with a spare cell. The flash memory device according to the present invention comprises a main memory cell array, a redundancy cell block, a redundancy row decoder, a row decoder, a column decoder, a flag bit cell block, a flag cell transfer gate, a main sense amplifier and a flag sense amplifier.
Inventors
- 👤 Joo Weon Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:53
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C7/00; G11C7/06; G11C7/062
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
141 words
A flash memory device comprising: a main cell array having a plurality of word lines and a plurality of bit lines; a column decoder for selecting any one of said bit lines; a row decoder for selecting any one of said word lines; a redundancy cell block connected between said bit lines and a plurality of spare word lines; a flag bit cell block coupled to said word lines, for storing whether any one word line of said word lines is failed or not; a flag sense amplifier coupled to a dummy bit line connected to a reference cell and said flag bit cell block; a redundancy row decoder for selecting said spare word lines in response to an output signal of the flag sense amplifier; and a main sense amplifier coupled to said dummy bit line and said column decoder.
Claim 2
Dependent Claim
141 words
A flash memory device comprising: a main cell array having a plurality of word lines and a plurality of bit lines; a column decoder for selecting any one of said bit lines; a row decoder for selecting any one of said word lines; a redundancy cell block connected between said bit lines and a plurality of spare word lines; a flag bit cell block coupled to said word lines, for storing whether any one word line of said word lines is failed or not; a flag sense amplifier coupled to a dummy bit line connected to a reference cell and said flag bit cell block; a redundancy row decoder for selecting said spare word lines in response to an output signal of the flag sense amplifier; and a main sense amplifier coupled to said dummy bit line and said column decoder.
Claim 3
Dependent Claim
25 words
The flash memory device claimed in claim 1 wherein said flag bit cell block is positioned within a guard ring of the main cell array.
Claim 4
Dependent Claim
20 words
The flash memory device claimed in claim 1 wherein said flag bit cell block is consisted of flash memory cells.
Claim 5
Dependent Claim
143 words
A flash memory device comprising: a main cell array having a plurality of word lines and a plurality of bit lines; a column decoder for selecting any one of said bit lines; a row decoder for selecting any one of said word lines; a redundancy cell block connected between said word lines and a plurality of spare bit lines; a flag bit cell block coupled to said column decoder, for storing whether any one bit line of said bit lines is failed or not; a flag sense amplifier coupled to a dummy bit line which is connected to a reference cell and said flag bit cell block; a redundancy column decoder for selecting said spare bit lines in response to an output signal of said flag sense amplifier; and a main sense amplifier coupled to said dummy bit line and said column decoder.
Claim 6
Dependent Claim
143 words
A flash memory device comprising: a main cell array having a plurality of word lines and a plurality of bit lines; a column decoder for selecting any one of said bit lines; a row decoder for selecting any one of said word lines; a redundancy cell block connected between said word lines and a plurality of spare bit lines; a flag bit cell block coupled to said column decoder, for storing whether any one bit line of said bit lines is failed or not; a flag sense amplifier coupled to a dummy bit line which is connected to a reference cell and said flag bit cell block; a redundancy column decoder for selecting said spare bit lines in response to an output signal of said flag sense amplifier; and a main sense amplifier coupled to said dummy bit line and said column decoder.
Claim 7
Dependent Claim
25 words
The flash memory device claimed in claim 4 wherein said flag bit cell block is positioned within a guard ring of the main cell array.
Claim 8
Dependent Claim
20 words
The flash memory device claimed in claim 4 wherein said flag bit cell block is consisted of flash memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |