Apparatus and method for providing notification of bit-cell failure in a redundant-bit-cell memory

Claim 1

In a digital memory in which a data bit is stored in each of at least three corresponding redundant bit-cells (designated ABC) so that an addressing operation retrieves redundant data bytes D A (1-N), D B (1-N), and D C (1-N) of N data bits;, a redundant-bit-cell error-flagging circuit, comprising: for each set of redundant data bits of an addressed data byte retrieved from the memory, an error-detector circuit for receiving three corresponding redundant data bits D A (N), D B (N), and D C (N) and providing a bit-cell-failure indication if said redundant data bits are not identical; an error-notification circuits responsive to the output from each error-detector circuit for providing an error-flag indication if any error-detection circuit outputs a bit-cell failure indication; said error-detector circuits and said error-flagging operation in accordance with a Boolean expression XOR C 1 XOR+A 2 XOR B 2 XOR C 2 XOR+. . .+A n XOR B n XOR C n XOR=EF, where (ABC) are the logic states for the three redundant data bits, and EF is the logic state of the output data bit the constitutes the error flag indication; such that a notification of bit-cell failure is provided if one of the redundant bit-cells inadvertently changes logic state.

Claim 11

A method of providing notification of bit-cell failure in a digital memory, in which a data bit is stored in each of at least three corresponding redundant-bit-cells, comprising the steps: retrieving from the memory redundant data bytes D A )1-N), D B (1-N) and D C (1-N) of N data bits; for each set of redundant data bits D A (N), D B (N), and D C (BN) of a retrieved data byte, detecting the logic state of each of the redundant data bits and generating a bit-cell-failure indication if said redundant data bits are not identical; and in response to the bit-cell-failure indication, generating an error notification; thereby implementing an error-flagging operation defined by the Boolean expression A 1 XOR B 1 XOR C 1 XOR+A x XOR B X XOR C 2 XOR+. . .+A x XOR B n XOR C n XOR=EF, where EF is an error notification.

Claim 12

A method of providing notification of bit-cell failure in a digital memory, in which a data bit is stored in each of at least three corresponding redundant-bit-cells, comprising the steps: retrieving from the memory redundant data bytes D A )1-N), D B (1-N) and D C (1-N) of N data bits; for each set of redundant data bits D A (N), D B (N), and D C (BN) of a retrieved data byte, detecting the logic state of each of the redundant data bits and generating a bit-cell-failure indication if said redundant data bits are not identical; and in response to the bit-cell-failure indication, generating an error notification; thereby implementing an error-flagging operation defined by the Boolean expression A 1 XOR B 1 XOR C 1 XOR+A x XOR B X XOR C 2 XOR+. . .+A x XOR B n XOR C n XOR=EF, where EF is an error notification.