US6791175B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked type semiconductor device
Assignee: Toshiba Corp
•
Filing: 2002-09-27
•
Granted: 2004-09-14
•
Expires: 2022-09-27
Abstract
Abstract Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.
Inventors
- 👤 Mie Matsuo
- 👤 Kenichi Imamiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:13
CPC Classifications
H; H10; H10W; H10W72/00; H10W90/00; H10W46/00; H10W46/401; H10W46/403; H10W90/20; H10W90/22; H10W90/284; H10W90/297; H10W90/701; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
112 words
A stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising: a holding circuit holding identification information about the chip, electrically written in the chip; an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked; and one or more setting terminals used to set the identification information about the chip, in the holding circuit; wherein said one or more setting terminals of any semiconductor integrated circuit chip are coupled to said one or more corresponding setting terminals of any other semiconductor integrated circuit chip.
Claim 2
Dependent Claim
112 words
A stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising: a holding circuit holding identification information about the chip, electrically written in the chip; an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked; and one or more setting terminals used to set the identification information about the chip, in the holding circuit; wherein said one or more setting terminals of any semiconductor integrated circuit chip are coupled to said one or more corresponding setting terminals of any other semiconductor integrated circuit chip.
Claim 3
Dependent Claim
22 words
The stacked type semiconductor device according to claim 1 , wherein the semiconductor integrated circuit chips have substantially the same circuit configuration.
Claim 4
Dependent Claim
64 words
The stacked type semiconductor device according to claim 1 , wherein each of the semiconductor integrated circuit chips further comprises at least one select terminal to which a signal for chip selection is input, and said at least one select terminal of any semiconductor integrated circuit chip is coupled to said at least one corresponding select terminal of any other semiconductor integrated circuit chip.
Claim 5
Dependent Claim
24 words
The stacked type semiconductor device according to claim 1 , wherein the holding circuit has a structure which allows information to be electrically rewritten.
Claim 6
Dependent Claim
19 words
The stacked type semiconductor device according to claim 1 , wherein the holding circuit includes a non-volatile memory cell.
Claim 7
Dependent Claim
44 words
The stacked type semiconductor device according to claim 1 , wherein the identification information setting circuit sets the identification information in the holding circuit on the basis of a difference between the semiconductor integrated circuit chips in time required to perform a predetermined operation.
Claim 8
Dependent Claim
27 words
The stacked type semiconductor device according to claim 6 , wherein the predetermined operation includes an operation of charging a capacitance in the semiconductor integrated circuit chip.
Claim 9
Dependent Claim
32 words
The stacked type semiconductor device according to claim 6 , wherein the predetermined operation includes a writing operation or an erasing operation for a memory cell in the semiconductor integrated circuit chip.
Claim 10
Dependent Claim
118 words
A stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising: a holding circuit configured to hold identification information about the chip, to be electrically written in the chip; an identification information setting circuit configured to set the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked; and one or more setting terminals used to set the identification information about the chip in the holding circuit; wherein said one or more setting terminals of any semiconductor integrated circuit chip are coupled to said one or more corresponding setting terminals of any other semiconductor integrated circuit chip.
Claim 11
Dependent Claim
118 words
A stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising: a holding circuit configured to hold identification information about the chip, to be electrically written in the chip; an identification information setting circuit configured to set the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked; and one or more setting terminals used to set the identification information about the chip in the holding circuit; wherein said one or more setting terminals of any semiconductor integrated circuit chip are coupled to said one or more corresponding setting terminals of any other semiconductor integrated circuit chip.
Claim 12
Dependent Claim
22 words
The stacked type semiconductor device according to claim 9 , wherein the semiconductor integrated circuit chips have substantially the same circuit configuration.
Claim 13
Dependent Claim
63 words
The stacked type semiconductor device according to claim 9 , wherein each of the semiconductor integrated circuit chips further comprises at least one select terminal which a signal for chip selection is input, and said at least one select terminal of any semiconductor integrated circuit chip is coupled to said at least one corresponding select terminal of any other semiconductor integrated circuit chip.
Claim 14
Dependent Claim
24 words
The stacked type semiconductor device according to claim 9 , wherein the holding circuit has a structure which allows information to be electrically rewritten.
Claim 15
Dependent Claim
24 words
The stacked type semiconductor device according to claim 9 , wherein the holding circuit includes a non-volatile memory cell or a volatile memory cell.
Claim 16
Dependent Claim
47 words
The stacked type semiconductor device according to claim 9 , wherein the identification information setting circuit is configured to set the identification information in the holding circuit on the basis of a difference between the semiconductor integrated circuit chips in time required to perform a predetermined operation.
Claim 17
Dependent Claim
27 words
The stacked type semiconductor device according to claim 14 , wherein the predetermined operation includes an operation of charging a capacitance in the semiconductor integrated circuit chip.
Claim 18
Dependent Claim
32 words
The stacked type semiconductor device according to claim 14 , wherein the predetermined operation includes a writing operation or an erasing operation for a memory cell in the semiconductor integrated circuit chip.
Claim 19
Dependent Claim
51 words
The stacked type semiconductor device according to claim 1 , wherein each of the semiconductor integrated circuit chips comprises a plurality of the setting terminals, and wherein said plurality of setting terminals of any semiconductor integrated circuit chip are coupled to corresponding setting terminals of any other semiconductor integrated circuit chip.
Claim 20
Dependent Claim
51 words
The stacked type semiconductor device according to claim 9 , wherein each of the semiconductor integrated circuit chips comprises a plurality of the setting terminals, and wherein said plurality of setting terminals of any semiconductor integrated circuit chip are coupled to corresponding setting terminals of any other semiconductor integrated circuit chip.
References Cited (Backward Citations)
US5928343A
Cited
US5581498A
Cited
JPH07283375A
Cited
US5640107A
Cited
JPH1097463A
Cited
US6239495B1
Cited
JP2001273755A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-09-14 | 2008-03-15 | 2008-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-09-14 | 2012-03-15 | 2012-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-09-14 | 2016-03-15 | 2016-09-14 | $7700.00 | Window Closed / Lapsed |