US6784101B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
Assignee: GlobalFoundries US Inc
•
Filing: 2002-05-16
•
Granted: 2004-08-31
•
Expires: 2022-05-16
Abstract
Abstract A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice therein, forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of the semiconductor substrate, and forming a layer of a high-k dielectric material on the thin buffer/interfacial layer of a low-k dielectric material. Embodiments include forming the thin buffer/interfacial layer and high-k layer at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.
Inventors
- 👤 Bin Yu
- 👤 David Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:14
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/66; H10P14/662; H10D; H10D30/00; H10D30/60; H10D30/751; H10D30/791; H10D30/798; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6938; H10P14/6939; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10D1/684
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
114 words
A method of manufacturing a semiconductor device, comprising sequential steps of: (a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof, said strained lattice semiconductor layer having a pre-sleeted amount of lattice strain therein; (b) forming a thin buffer/interfacial layer of a low-k dielectric material on said upper surface of said semiconductor substrate; and (c) forming a layer of a high-k dielectric material on said thin buffer/interfacial layer of a low-k dielectric material, wherein: steps (b) and (c) are each performed at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of said strained lattice semiconductor layer.
Claim 2
Independent Claim
114 words
A method of manufacturing a semiconductor device, comprising sequential steps of: (a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof, said strained lattice semiconductor layer having a pre-sleeted amount of lattice strain therein; (b) forming a thin buffer/interfacial layer of a low-k dielectric material on said upper surface of said semiconductor substrate; and (c) forming a layer of a high-k dielectric material on said thin buffer/interfacial layer of a low-k dielectric material, wherein: steps (b) and (c) are each performed at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of said strained lattice semiconductor layer.
Claim 3
Dependent Claim
44 words
The method as in claim 1 , wherein: step (a) comprises providing a semiconductor substrate including a crystalline, graded composition Si—Ge layer, with a lattice-matched crystalline silicon (Si) layer on a first side of said Si—Ge layer and comprising said strained lattice semiconductor layer.
Claim 4
Dependent Claim
30 words
The method as in claim 2 , wherein: step (a) further comprises providing a semiconductor substrate including a crystalline Si layer on a second, opposite side of said Si—Ge layer.
Claim 5
Dependent Claim
29 words
The method as in claim 1 , wherein: step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material having a dielectric constant k less than 5.
Claim 6
Dependent Claim
31 words
The method as in claim 4 , wherein: step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material at a thickness from about 2 to about 6 Å.
Claim 7
Dependent Claim
37 words
The method as in claim 4 , wherein: step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material from at least one material selected from the group consisting of silicon oxides and silicon oxynitrides.
Claim 8
Dependent Claim
32 words
The method as in claim 5 , wherein: step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material at a temperature ranging from about 200 to about 400° C.
Claim 9
Dependent Claim
43 words
The method as in claim 7 , wherein: step (b) comprises forming said thin buffer/interfacial layer of a low-k dielectric material by an atomic layer deposition (ALD) method selected from chemical vapor deposition (CVD), molecular beam deposition (MBD), and physical vapor deposition (PVD).
Claim 10
Dependent Claim
27 words
The method as in claim 1 , wherein: step (c) comprises forming said layer of a high-k dielectric material having a dielectric constant k greater than 5.
Claim 11
Dependent Claim
29 words
The method as in claim 9 , wherein: step (c) comprises forming said layer of a high-k dielectric material at a thickness from about 40 to about 100 Å.
Claim 12
Dependent Claim
52 words
The method as in claim 9 , wherein: step (c) comprises forming said layer of a high-k dielectric material from at least one metal and oxygen-containing material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and tenary metal oxides.
Claim 13
Dependent Claim
105 words
The method as in claim 11 , wherein: step (c) comprises forming said layer of a high-k dielectric material from at least one material selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, tungsten oxide, cerium oxide, yttrium oxide, zirconium silicate, hafnium silicate, hafnium aluminae, lathanum aluminate, lead titanate, barium titanate, strontium titanate, barium strontium titante, lead zirconate; ferroelectric oxides, ternary metal oxides, PST (PbSc x Ta 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), PZT (PbZ r Ti 1−x O 3 ), and PMN (PbMg x Nb 1−x O 3 ).
Claim 14
Dependent Claim
30 words
The method as in claim 9 , wherein: step (c) comprises forming said layer of a high-k dielectric material at a temperature ranging from about 200 to about 400° C.
Claim 15
Dependent Claim
41 words
The method as in claim 13 , wherein: step (c) comprises forming said layer of a high-k dielectric material by an atomic layer deposition (ALD) method selected from chemical vapor deposition (CVD), molecular beam disposition (MBD), and physical vapor deposition (PVD).
Claim 16
Dependent Claim
73 words
The method as in claim 1 , further comprising sequential steps of: (d) forming an electrically conductive layer on said layer of a high-k dielectric material; and (e) patterning said electrically conductive layer, said layer of a high-k dielectric material, and said thin buffer layer of a low-k dielectric material to form at least one gate insulator layer/gate electrode stack on at least one portion of said upper surface of said semiconductor substrate.
Claim 17
Dependent Claim
70 words
The method as in claim 15 , further comprising the step of: (f) implanting dopant species of one conductivity type into said semiconductor substrate utilizing said at least one gate insulator layer/gate electrode stack as an implantation mask, thereby forming at least one pair of shallow depth source/drain extension regions in said semiconductor substrate vertically aligned with opposite side edges of said at least one gate insulator layer/gate electrode stack.
Claim 18
Dependent Claim
143 words
The method as in claim 16 , further comprising sequential steps of: (g) forming insulative sidewall spacers on said opposite side edges of said at least one gate insulator layer/gate electrode stack; (h) implanting dopant species of said one conductivity type into said semiconductor substrate utilizing said at least one gate insulator layer/gate electrode stack with said insulative sidewall spacers thereon as an implantation mask, thereby forming at least one pair of deeper source/drain regions in said semiconductor substrate vertically aligned with opposite side edges of said sidewall spacers; and (i) thermally annealing the thus-formed structure for a minimum interval sufficient to activate said dopant species implanted in said at least one pair of shallow depth source/drain regions and in said at least one pair of deeper source/drain regions without incurring, or at least minimizing, strain relaxation of said strained lattice semiconductor layer.
Claim 19
Dependent Claim
39 words
The method as in claim 17 , wherein: step (i) comprises performing laser thermal annealing (LTA) or rapid thermal annealing (RTA) at a temperature from about 1,200 to about 1,400° C. for from about 1 to about 100 nanosec.
Claim 20
Dependent Claim
14 words
A PMOS or NMOS transistor manufactured according to the method of claim 18 .
Claim 21
Dependent Claim
14 words
A CMOS or IC device manufactured according to the method of claim 18 .
References Cited (Backward Citations)
US4181538A
Cited
US6063698A
Cited
EP0973189A2
Cited
US6100204A
Cited
US6197641B1
Cited
US6444592B1
Cited
US6509587B2
Cited
US20020100942A1
Cited
US20030049942A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-08-31 | 2008-03-01 | 2008-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-08-31 | 2012-03-01 | 2012-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-08-31 | 2016-03-01 | 2016-08-31 | $7700.00 | Window Closed / Lapsed |