Vertically stacked memory chips in FBGA packages

Claim 2

A memory structure comprising: a plurality of adjacent substrates stacked one on another; a plurality of connectors connecting said substrates to one another a memory chip package mounted on each of said substrates; a first gap between a top or said memory chip package end a bottom of an adjacent substrate; wherein said connectors have a size sufficient to form a second gap between said substrates; wherein said second gap is larger than a height of said memory chip package; and wherein said connectors comprises solder balls arranged in a fine ball grid array.

Claim 3

The memory structure in claim 1 , wherein said memory chip package comprises a pre-tested memory chip package that is tested for defects before being mounted on said substrates.

Claim 4

The memory structure in claim 1 , wherein said memory chip package and said substrates includes identical electrical connections.

Claim 5

The memory structure in claim 1 , wherein each of said substrates has a plurality of said memory chip package mounted thereon.

Claim 6

The memory structure in claim 1 , further comprising a thermal material between a top of said memory chip package and a bottom of an adjacent substrate.

Claim 7

The memory structure in claim 1 , wherein said memory chip package comprises a chip having an array of memory elements mounted within a package.

Claim 8

A memory structure comprising: a plurality of adjacent substrates stacked one on another; a plurality of connectors connecting said substrates to one another; a memory chip package mounted on each of said substrates; a first gap between a top of said memory chip package and a bottom of an adjacent substrate; wherein said connectors have a size sufficient to form a second gap between said substrates; wherein said second gap is larger than a height of said memory chip package; wherein each memory chip package includes only a single memory chip; and wherein said connectors comprises solder balls arranged in a fine ball grid array.

Claim 9

A memory structure comprising: a plurality of adjacent substrates stacked one on another; a plurality of connectors connecting said substrates to one another; a memory chip package mounted on each of said substrates; a first gap between a top of said memory chip package and a bottom of an adjacent substrate; wherein said connectors have a size sufficient to form a second gap between said substrates; wherein said second gap is larger than a height of said memory chip package; wherein each memory chip package includes only a single memory chip; and wherein said connectors comprises solder balls arranged in a fine ball grid array.

Claim 10

The memory structure in claim 7 , wherein said memory chip package comprises a pre-tested memory chip package that is tested for defects before being mounted on said substrates.

Claim 11

The memory structure in claim 7 , wherein said memory chip package and said substrates include identical electrical connections.

Claim 12

The memory structure in claim 7 , wherein each of said substrates has a plurality of said memory chip packages mounted thereon.

Claim 13

The memory structure in claim 7 , further comprising a thermal material between a top of said memory chip package and a bottom of an adjacent substrate.

Claim 14

The memory structure in claim 7 , wherein said memory chip package comprises a chip having an array of memory elements mounted within a package.

Claim 15

A vertically stacked memory module comprising: a plurality of adjacent substrates stacked one on another; a plurality of substrate spacers electrically connecting said substrates with one another; a single memory chip package mounted on each of said substrates; a plurality of package spacers connecting said memory chip package with said substrates; a first gap between a top of said memory chip package and a bottom of an adjacent substrate; wherein said memory chip package comprises a memory chip having an array of memory elements mounted within said package; wherein said substrate spacers form a second gap between a top of said memory chip package and a bottom of said adjacent substrates; wherein said second gap is greater than a height of said memory chip package; and wherein said substrate spacers and said package spacers comprise solder balls arranged in a fine ball arid array.

Claim 16

A vertically stacked memory module comprising: a plurality of adjacent substrates stacked one on another; a plurality of substrate spacers electrically connecting said substrates with one another; a single memory chip package mounted on each of said substrates; a plurality of package spacers connecting said memory chip package with said substrates; a first gap between a top of said memory chip package and a bottom of an adjacent substrate; wherein said memory chip package comprises a memory chip having an array of memory elements mounted within said package; wherein said substrate spacers form a second gap between a top of said memory chip package and a bottom of said adjacent substrates; wherein said second gap is greater than a height of said memory chip package; and wherein said substrate spacers and said package spacers comprise solder balls arranged in a fine ball arid array.

Claim 17

The memory module in claim 13 , wherein said memory chip package comprises a pre-tested memory chip package that is tested for defects before being mounted on said substrates.

Claim 18

The memory module in claim 13 , wherein said memory chip package and said substrates include identical electrical connections.

Claim 19

The memory module in claim 13 , wherein each of said substrates has a plurality of said memory chip packages mounted thereon.

Claim 20

The memory module in claim 13 , further comprising thermal material between a top of said memory chip package and a bottom of an adjacent substrate.