US6765976B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay-locked loop for differential clock signals
Assignee: RPX Corp
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Filing: 2000-09-13
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Granted: 2004-07-20
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Expires: 2020-09-13
Abstract
Abstract A significantly more efficient implementation of a DLL for systems using two separate clock signals, whereby a single DLL circuit is used to provide for locking of both clock signals. According to the present invention, the input to the DLL is controlled such that it responds to edges of both clock signals. The present invention provides a circuit receiving a first periodic signal CLK 1 and a second periodic signal CLK 2 , there being a phase difference between CLK 1 and CLK 2 , the circuit including a delay-locked loop (DLL) having one delay path, wherein the same delay path provides delay tuning for both CLK 1 and CLK 2.
Inventors
- 👤 Jong-Hoon Oh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:04
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/0818; H03L7/085; H03L7/087; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0896
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
138 words
A circuit receiving a first periodic signal CLK 1 and a second periodic signal CLK 2 , there being a phase difference between CLK 1 and CLK 2 , the circuit comprising a delay-locked loop (DLL) coupled to receive CLK 1 and CLK 2 and configured to generate periodic signals C_IN 1 and C_IN 2 such that: C_IN 1 makes a first transition in response to a rising edge of CLK 1 and a second transition in response to a rising edge of CLK 2 , and C_IN 2 makes a first transition in response to a rising edge of CLK 2 and a second transition in response to a rising edge of CLK 1 , the DLL having one delay path, wherein the same delay path provides delay tuning for both CLK 1 and CLK 2 .
Claim 2
Dependent Claim
138 words
A circuit receiving a first periodic signal CLK 1 and a second periodic signal CLK 2 , there being a phase difference between CLK 1 and CLK 2 , the circuit comprising a delay-locked loop (DLL) coupled to receive CLK 1 and CLK 2 and configured to generate periodic signals C_IN 1 and C_IN 2 such that: C_IN 1 makes a first transition in response to a rising edge of CLK 1 and a second transition in response to a rising edge of CLK 2 , and C_IN 2 makes a first transition in response to a rising edge of CLK 2 and a second transition in response to a rising edge of CLK 1 , the DLL having one delay path, wherein the same delay path provides delay tuning for both CLK 1 and CLK 2 .
Claim 3
Dependent Claim
62 words
The circuit of claim 1 wherein the DLL further has a delay tuning circuit that is coupled to receive C_IN 1 and C_IN 2 and to generate output signals OUT_CLK 1 and OUT_CLK 2 , the delay tuning circuit having compare circuitry to compare a phase difference between C_IN 1 and OUT_CLK 1 , and between C_IN 2 and OUT_CLK 2 .
Claim 4
Dependent Claim
22 words
The circuit of claim 2 wherein the delay tuning circuit includes a coarse delay tuning stage and a fine delay tuning stage.
Claim 5
Dependent Claim
36 words
The circuit of claim 3 wherein the coarse delay tuning stage includes: a coarse delay tuning circuit; a shift register coupled to the coarse delay tuning circuit; and a phase detector coupled to the shift register.
Claim 6
Dependent Claim
17 words
The circuit of claim 4 wherein the coarse delay tuning circuit includes a plurality of delay cells.
Claim 7
Dependent Claim
27 words
The circuit of claim 5 wherein a delay cell of the coarse delay tuning circuit is a digital delay cell including: a NAND gate; and an inverter.
Claim 8
Dependent Claim
36 words
The circuit of claim 3 wherein the fine delay tuning stage includes: a fine delay tuning circuit; a charge pump coupled to the fine delay tuning circuit; and a phase detector coupled to the charge pump.
Claim 9
Dependent Claim
17 words
The circuit of claim 7 wherein the fine delay tuning circuit includes a plurality of delay cells.
Claim 10
Dependent Claim
36 words
The circuit of claim 8 wherein a delay cell of the fine delay tuning circuit is an analog delay cell including: a gate, the delay of which is controlled by the amount of current flowing therethrough.
Claim 11
Dependent Claim
44 words
The circuit of claim 8 , further including logic to ensure that rising and falling edges of a signal propagating through the delay cells of the fine delay tuning circuit are delayed equally, whereby a substantially constant duty cycle of the signal is maintained.
Claim 12
Dependent Claim
118 words
The circuit of claim 1 wherein the DLL further has a phase detector, the phase detector comprising: a logic block; a first compare block connected to the logic block; a second compare block connected to the logic block; and a digital delay cell connected to the second compare block; wherein the first compare block receives an input clock signal and an output clock signal and outputs a signal to the logic block representing a lead or a lag, the second compare block receives the input clock signal and the output clock signal and outputs a signal to the logic block representing a lead or a lag, and wherein the logic block outputs a signal to a shift register.
Claim 13
Dependent Claim
130 words
A circuit receiving a first periodic signal CLK 1 and a second periodic signal CLK 2 there being a phase difference between CLK 1 and CLK 2 , the circuit comprising a delay-locked loop (DLL) having: a first clock input circuit coupled to receive CLK 1 and CLK 2 and configured to generate a first periodic signal that is set by a first edge of CLK 1 and reset by a first edge of CLK 2 ; second clock input circuit coupled to receive CLK 1 and CLK 2 and configured to generate a second periodic signal that is set by a first edge of CLK 2 and reset by a first edge of CLK 1 ; and a delay path configured to process the first and second periodic signals.
Claim 14
Dependent Claim
130 words
A circuit receiving a first periodic signal CLK 1 and a second periodic signal CLK 2 there being a phase difference between CLK 1 and CLK 2 , the circuit comprising a delay-locked loop (DLL) having: a first clock input circuit coupled to receive CLK 1 and CLK 2 and configured to generate a first periodic signal that is set by a first edge of CLK 1 and reset by a first edge of CLK 2 ; second clock input circuit coupled to receive CLK 1 and CLK 2 and configured to generate a second periodic signal that is set by a first edge of CLK 2 and reset by a first edge of CLK 1 ; and a delay path configured to process the first and second periodic signals.
Claim 15
Dependent Claim
31 words
The circuit of claim 12 wherein the delay path is configured to substantially maintain a duty ratio of the first and second periodic signals as they propagate through the delay path.
Claim 16
Dependent Claim
21 words
The circuit of claim 13 wherein the delay path includes a coarse delay tuning block and a fine delay tuning block.
Claim 17
Dependent Claim
29 words
The circuit of claim 13 wherein the circuit includes a synchronous memory circuit operating in response to a differential clock signal made of CLK 1 and CLK 2 .
Claim 18
Dependent Claim
21 words
The circuit of claim 15 wherein feedback loops in the delay path include delay circuits configured to track memory access delay.
Claim 19
Independent Claim
96 words
A method of tuning delay of two out-of-phase periodic signals, CLK 1 and CLK 2 , the method comprising: combining CLK 1 and CLK 2 to generate a first periodic signal C_IN 1 with a rising edge determined by CLK 1 and a falling edge determined by CLK 2 ; and applying C_IN 1 to a delay-locked loop having a delay path that substantially maintains a duty ratio of C_IN 1 , whereby the delay-locked loop generates output signals, OUT_CLK 1 and OUT_CLK 2 , that are delay-tuned to CLK 1 and CLK 2 , respectively.
Claim 20
Independent Claim
96 words
A method of tuning delay of two out-of-phase periodic signals, CLK 1 and CLK 2 , the method comprising: combining CLK 1 and CLK 2 to generate a first periodic signal C_IN 1 with a rising edge determined by CLK 1 and a falling edge determined by CLK 2 ; and applying C_IN 1 to a delay-locked loop having a delay path that substantially maintains a duty ratio of C_IN 1 , whereby the delay-locked loop generates output signals, OUT_CLK 1 and OUT_CLK 2 , that are delay-tuned to CLK 1 and CLK 2 , respectively.
Claim 21
Dependent Claim
64 words
The method of claim 17 , the method further comprising: combining CLK 1 and CLK 2 to generate a second periodic signal C_IN 2 with a rising edge determined by CLK 2 and a falling edge determined by CLK 1 ; and applying C_IN 2 to a delay-locked loop having a delay path that substantially maintains a duty ratio of signal C_IN 2 .
Claim 22
Dependent Claim
30 words
The method of claim 18 , the method further comprising: performing delay tuning by applying C_IN 1 , C_IN 2 , OUT_CLK 1 and OUT_CLK 2 to delay tuning circuitry.
Claim 23
Dependent Claim
19 words
The method of claim 19 wherein performing delay tuning includes: performing coarse delay tuning; and performing fine delay tuning.
Claim 24
Dependent Claim
58 words
The method of claim 20 wherein performing coarse delay tuning includes: receiving C_IN 1 and OUT_CLK 1 into a first phase detector circuit; comparing the phase difference between C_IN 1 and OUT_CLK 1 via the first phase detector circuit; and adjusting the delay of C_IN 1 depending upon the phase difference between C_IN 1 and OUT_CLK 1 .
Claim 25
Dependent Claim
102 words
The method of claim 20 wherein performing fine delay tuning includes: receiving C_IN 1 and OUT_CK 1 into a second phase detector circuit; receiving C_IN 2 and OUT_CK 2 into a third phase detector circuit; comparing the phases of C_IN 1 and OUT_CK 1 via the second phase detector circuit; comparing the phases of C_IN 2 and OUT_CK 2 via the third phase detector circuit; adjusting the delay of OUT_CK 1 depending upon the phase difference between C_IN 1 and OUT_CK 1 ; and adjusting the delay of OUT_CK 2 depending upon the phase difference between C_IN 2 and OUT_CK 2 .
Claim 26
Dependent Claim
63 words
An integrated circuit memory device comprising: a delay-locked loop (DLL) circuit coupled to receive two periodic signals CLK 1 and CLK 2 and configured to generate two periodic clock signals OUT_CLK 1 and OUT_CLK 2 , the DLL circuit comprising one delay path configured to provide delay tuning both between OUT_CLK 1 and CLK 1 and between OUT_CLK 2 and CLK 2 .
Claim 27
Dependent Claim
63 words
An integrated circuit memory device comprising: a delay-locked loop (DLL) circuit coupled to receive two periodic signals CLK 1 and CLK 2 and configured to generate two periodic clock signals OUT_CLK 1 and OUT_CLK 2 , the DLL circuit comprising one delay path configured to provide delay tuning both between OUT_CLK 1 and CLK 1 and between OUT_CLK 2 and CLK 2 .
Claim 28
Dependent Claim
19 words
The integrated circuit memory device of claim 23 wherein the two external clock signals form a differential clock signal.
Claim 29
Dependent Claim
98 words
The integrated circuit memory device of claim 23 further comprising: an input clock circuit coupled to receive CLK 1 and CLK 2 and configured to generate periodic signals C_IN 1 and C_IN 2 , wherein the signal C_IN 1 makes a first transition in response to a rising edge of CLK 1 and a second transition in response to a rising edge of CLK 2 , and the signal C_IN 2 makes a first transition in response to a rising edge of CLK 2 and a second transition in response to a rising edge of CLK 1 .
Claim 30
Dependent Claim
63 words
The integrated circuit memory device of claim 25 wherein the DLL further includes a delay tuning circuit that is coupled to receive C_IN 1 and C_IN 2 and to generate OUT_CLK 1 and OUT_CLK 2 , the delay tuning circuit having compare circuitry to compare a phase difference between C_IN 1 and OUT_CLK 1 , and between C_IN 2 and OUT_CLK 2 .
Claim 31
Dependent Claim
29 words
The integrated circuit memory device of claim 23 wherein the DLL includes a coarse delay tuning stage and a fine delay tuning stage configured to provide the delay tuning.
Claim 32
Dependent Claim
39 words
The integrated circuit memory device of claim 27 wherein the coarse delay tuning stage includes: a coarse delay tuning circuit; a shift register coupled to the coarse delay tuning circuit; and a phase detector coupled to the shift register.
Claim 33
Dependent Claim
36 words
The integrated circuit memory device of claim 27 wherein the fine includes: a fine delay tuning circuit; a charge pump coupled to the fine delay tuning circuit; and a phase detector coupled to the charge pump.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-07-20 | 2008-01-19 | 2008-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-07-20 | 2012-01-19 | 2012-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-07-20 | 2016-01-19 | 2016-07-20 | $7700.00 | Window Closed / Lapsed |