US6765825B1
Expired / Lapsed
US
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Differential nor memory cell having two floating gate transistors
Assignee: AMI Semiconductor Inc
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Filing: 2003-03-12
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Granted: 2004-07-20
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Expires: 2023-03-12
Abstract
Abstract An EEPROM memory cell that includes two floating gate transistors. Each of the drain terminals of the transistors is coupled to a corresponding differential bit line. The source terminal of both transistors are coupled to a common current source or sink. Each of the control gate terminals are coupled to a corresponding word line, which may be the same as or different than the corresponding word line that the other control terminal is connected to. The floating gate transistor may be five-terminal devices that include an additional well terminal. In that case, a different set of bit lines is used to program the EEPROM memory cell as are used to read the EEPROM memory cell. While the drain terminals are coupled to the differential read bit lines, each of the well terminals is coupled to a corresponding differential program bit line.
Inventors
- 👤 Greg Scott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:23
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
167 words
A differential Electrically-Erasable and Programmable Read-Only Memory (EEPROM) memory in which a memory cell comprises: a first floating gate transistor comprising a first control gate terminal, a first floating gate, a first source terminal, and a first drain terminal, the first drain terminal coupled to a first differential bit line, the first control gate terminal coupled to a first word line, the first source terminal coupled to a current source or sink; and a second floating gate transistor comprising a second control gate terminal, a second floating gate, a second source terminal, and a second drain terminal, the second drain terminal coupled to a second differential bit line, the second control gate terminal coupled to a second word line, the second source terminal coupled to the current source or sink, wherein the memory further comprises a circuit component configured to identify a binary bit stored by the memory cell depending on which of the first or second floating gate transistors draws more current during a read operation.
Claim 2
Dependent Claim
167 words
A differential Electrically-Erasable and Programmable Read-Only Memory (EEPROM) memory in which a memory cell comprises: a first floating gate transistor comprising a first control gate terminal, a first floating gate, a first source terminal, and a first drain terminal, the first drain terminal coupled to a first differential bit line, the first control gate terminal coupled to a first word line, the first source terminal coupled to a current source or sink; and a second floating gate transistor comprising a second control gate terminal, a second floating gate, a second source terminal, and a second drain terminal, the second drain terminal coupled to a second differential bit line, the second control gate terminal coupled to a second word line, the second source terminal coupled to the current source or sink, wherein the memory further comprises a circuit component configured to identify a binary bit stored by the memory cell depending on which of the first or second floating gate transistors draws more current during a read operation.
Claim 3
Dependent Claim
21 words
An EEPROM memory in accordance with claim 1 , wherein the first and second word lines are the same word line.
Claim 4
Dependent Claim
20 words
An EEPROM memory in accordance with claim 1 , wherein the first and second word lines are different word lines.
Claim 5
Dependent Claim
29 words
An EEPROM memory in accordance with claim 1 , wherein the first and second floating gate transistors are n-type and the current source or sink is a current sink.
Claim 6
Dependent Claim
29 words
An EEPROM memory in accordance with claim 1 , wherein the first and second floating gate transistors are p-type and the current source or sink is a current source.
Claim 7
Dependent Claim
164 words
A differential Electrically-Erasable and Programmable Read-Only Memory EEPROM memory cell comprising the following: a first five-terminal floating gate transistor comprising a first control gate terminal, a first floating gate, a first source terminal, a first drain terminal, and a first well terminal, the first drain terminal coupled to a first differential read bit line, the first well terminal coupled to a first differential program bit line, the first control gate terminal coupled to a first word line, the first source terminal coupled to a current source or sink; and a second five-terminal floating gate transistor comprising a second control gate terminal, a second floating gate, a second source terminal, a second drain terminal, and a second well terminal, the second drain terminal coupled to a second differential read bit line, the second well terminal coupled to a second differential program bit line, the second control gate terminal coupled to a second word line, the second source terminal coupled to the current source or sink.
Claim 8
Dependent Claim
164 words
A differential Electrically-Erasable and Programmable Read-Only Memory EEPROM memory cell comprising the following: a first five-terminal floating gate transistor comprising a first control gate terminal, a first floating gate, a first source terminal, a first drain terminal, and a first well terminal, the first drain terminal coupled to a first differential read bit line, the first well terminal coupled to a first differential program bit line, the first control gate terminal coupled to a first word line, the first source terminal coupled to a current source or sink; and a second five-terminal floating gate transistor comprising a second control gate terminal, a second floating gate, a second source terminal, a second drain terminal, and a second well terminal, the second drain terminal coupled to a second differential read bit line, the second well terminal coupled to a second differential program bit line, the second control gate terminal coupled to a second word line, the second source terminal coupled to the current source or sink.
Claim 9
Dependent Claim
22 words
An EEPROM memory cell in accordance with claim 6 , wherein the first and second word lines are the same word line.
Claim 10
Dependent Claim
21 words
An EEPROM memory cell in accordance with claim 6 , wherein the first and second word lines are different word lines.
Claim 11
Dependent Claim
30 words
An EEPROM memory cell in accordance with claim 6 , wherein the first and second floating gate transistors are n-type and the current source or sink is a current sink.
Claim 12
Dependent Claim
17 words
An EEPROM memory cell in accordance with claim 9 , wherein the first well terminal is n-type.
Claim 13
Dependent Claim
17 words
An EEPROM memory cell in accordance with claim 10 , wherein the second well terminal is n-type.
Claim 14
Dependent Claim
17 words
An EEPROM memory cell in accordance with claim 9 , wherein the first well terminal is p-type.
Claim 15
Dependent Claim
17 words
An EEPROM memory cell in accordance with claim 12 , wherein the second well terminal is n-type.
Claim 16
Dependent Claim
19 words
An EEPROM memory cell in accordance with claim 9 , wherein the first and second well terminals are p-type.
Claim 17
Dependent Claim
30 words
An EEPROM memory cell in accordance with claim 6 , wherein the first and second floating gate transistors are n-type and the current source or sink is a current sink.
Claim 18
Dependent Claim
30 words
An EEPROM memory cell in accordance with claim 6 , wherein the first and second floating gate transistors are p-type and the current source or sink is a current source.
Claim 19
Dependent Claim
17 words
An EEPROM memory cell in accordance with claim 6 , wherein the first well terminal is p-type.
Claim 20
Dependent Claim
17 words
An EEPROM memory cell in accordance with claim 16 , wherein the second well terminal is p-type.
Claim 21
Dependent Claim
17 words
An EEPROM memory cell in accordance with claim 16 , wherein the second well terminal is n-type.
Claim 22
Dependent Claim
19 words
An EEPROM memory cell in accordance with claim 16 , wherein the first and second well terminals are p-type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-07-20 | 2008-01-19 | 2008-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-07-20 | 2012-01-19 | 2012-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-07-20 | 2016-01-19 | 2016-07-20 | $7700.00 | Window Closed / Lapsed |