US6358799B2
Expired / Lapsed
US
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Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device
Assignee: Panasonic Holdings Corp
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Filing: 2000-12-04
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Granted: 2002-03-19
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Expires: 2020-12-04
Abstract
Abstract In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.
Inventors
- 👤 Shinji Odanaka
- 👤 Kaori Akamatsu
- 👤 Junichi Kato
- 👤 Atsushi Hori
- 👤 Seiki Ogura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:47
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
191 words
A method for fabricating a nonvolatile semiconductor memory device, comprising the steps of: forming an insulating film on a substrate; forming a control gate on the insulating film; forming a sidewall on a side of the control gate, etching the substrate using a first mask pattern comprising the control gate, the sidewall and a mask material, such that the substrate has a first surface region at a first level, a second surface region at a second level lower than the first level and a step side region, the step side region linking the first and second surface regions together and being aligned with one edge of the sidewall; forming a low-concentration impurity layer which function as a part of a drain region, the low-concentration impurity layer extending in the substrate so as to cover a corner portion between the second surface region and the step side region and not to reach the first surface region, wherein the upper portion of the step side region functions as a part of the channel region; removing the sidewall; and forming a floating gate adjacent to the control gate and covering the step side region.
Claim 2
Independent Claim
191 words
A method for fabricating a nonvolatile semiconductor memory device, comprising the steps of: forming an insulating film on a substrate; forming a control gate on the insulating film; forming a sidewall on a side of the control gate, etching the substrate using a first mask pattern comprising the control gate, the sidewall and a mask material, such that the substrate has a first surface region at a first level, a second surface region at a second level lower than the first level and a step side region, the step side region linking the first and second surface regions together and being aligned with one edge of the sidewall; forming a low-concentration impurity layer which function as a part of a drain region, the low-concentration impurity layer extending in the substrate so as to cover a corner portion between the second surface region and the step side region and not to reach the first surface region, wherein the upper portion of the step side region functions as a part of the channel region; removing the sidewall; and forming a floating gate adjacent to the control gate and covering the step side region.
Claim 3
Dependent Claim
94 words
The method for fabricating a nonvolatile semiconductor memory device of claim 1 , further comprising, after the step of forming the control gate and before the step of forming the floating gate, the step of: increasing an impurity concentration of a portion of a channel region formed in the substrate, the portion close to the step side region, by implanting impurity ions of conductivity type opposite to that of the drain region into the substrate using a second mask pattern comprising the control gate, thereby forming a high-concentration impurity layer in the channel region.
Claim 4
Dependent Claim
109 words
The method for fabricating a nonvolatile semiconductor memory device of claim 1 , further comprising, after the step of forming the control gate and before the step of forming the floating gate, the step of: increasing an impurity concentration of a portion of a channel region formed in the substrate, the portion close to the step side region, by implanting impurity ions of conductivity type opposite to that of the drain region into the substrate through an opening of a third mask pattern comprising the control gate and the same mask material as comprised in the first mask pattern, thereby forming a high-concentration impurity layer in the channel region.
Claim 5
Dependent Claim
33 words
The method for fabricating a nonvolatile semiconductor memory device of claim 2 , wherein the impurity ions are implanted to form the high-concentration impurity layer before the step of etching of the substrate.
Claim 6
Dependent Claim
33 words
The method for fabricating a nonvolatile semiconductor memory device of claim 3 , wherein the impurity ions are implanted to form the high-concentration impurity layer before the step of etching of the substrate.
Claim 7
Dependent Claim
32 words
The method for fabricating a nonvolatile semiconductor memory device of claim 2 , wherein the impurity ions are implanted to form the high-concentration impurity layer after the step of etching the substrate.
Claim 8
Dependent Claim
32 words
The method for fabricating a nonvolatile semiconductor memory device of claim 3 , wherein the impurity ions are implanted to form the high-concentration impurity layer after the step of etching the substrate.
Claim 9
Dependent Claim
56 words
The method for fabricating a nonvolatile semiconductor memory device of claim 1 , further comprising, after the step of etching the substrate and before the step of forming the floating gate, the step of: forming an extremely-low-concentration impurity layer in a channel region formed in the substrate by implanting impurity ions into the step side region.
Claim 10
Dependent Claim
29 words
The method for fabricating a nonvolatile semiconductor memory device of claim 8 , wherein the extremely-low-concentration impurity layer has a conductivity type opposite to that of the drain region.
Claim 11
Dependent Claim
29 words
The method for fabricating a nonvolatile semiconductor memory device of claim 8 , wherein the extremely-low-concentration impurity layer has the same conductivity type as that of the drain region.
Claim 12
Dependent Claim
105 words
The method for fabricating a nonvolatile semiconductor memory device of claim 1 , further comprising, after the step of forming the control gate and before the step of forming the floating gate, the step of: decreasing an impurity concentration of a portion of a channel region in the substrate, the portion adjacent to the drain region, which has a conductivity type opposite to that of the drain region, by implanting impurity ions of the same conductivity type as that of the drain region into the substrate using a second mask pattern comprising the control gate, thereby forming an extremely-low-concentration impurity layer in the channel region.
Claim 13
Dependent Claim
46 words
The method for fabricating a nonvolatile semiconductor memory device of claim 11 , wherein the conductivity type of the extremely-low-concentration impurity layer is made opposite to that of the drain region by implanting ions into the substrate without reversing the conductivity type of the channel region.
Claim 14
Dependent Claim
48 words
The method of fabricating a nonvolatile semiconductor memory device of claim 11 , wherein the conductivity type of the extremely-low-concentration impurity layer is made the same as that of the drain region by implanting impurity ions into the substrate to reverse the conductivity type of the channel region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-03-18 | 2005-09-17 | 2006-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-18 | 2009-09-17 | 2010-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-18 | 2013-09-17 | 2014-03-19 | $7700.00 | Window Closed / Lapsed |