EP0847091A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Low voltage eeprom/nvram transistors and making method
Assignee: Halo LSI Design and Device Technology Inc
•
Filing: 1997-12-08
•
Granted: —
•
Expires: 2017-12-08
Abstract
Abstract An electrically programmable memory device which has greater efficiency of electron injection from the channel to the floating gate comprises a substrate (401) having source (404) and drain (406) regions with a channel (410,413) therebetween; a floating gate structure over portions of the source (404) and drain (406) regions and the channel (410,413), which structure includes a dielectric layer (420) and a conductor layer (440) thereover; the channel under the floating gate (440) having both horizontal (410) and vertical (413) components. <IMAGE>
Inventors
- 👤 Seiki Ogura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 21:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10B; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B41/30; H10B69/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
70 words
An electrically programmable memory device which has greater efficiency of
electron injection from the channel to the floating gate comprising: a substrate having source and drain regions with a channel therebetween; a floating gate structure over portions of said source and drain regions and said
channel, which structure includes a dielectric layer and a conductor layer thereover; and
said channel under said floating gate having both horizontal and vertical components.
Claim 2
Dependent Claim
78 words
The electronically programmabe memory device of claim 1 wherein said horizontal
and vertical components are a horizontal channel and a vertical channel, and the said
vertical channel is adjacent to said drain region and said horizontal is adjacent to said
source region which device provides in operation accelerated electrons in the horizontal
channel are injected straight in the direction of momentum into the vertical channel and
the vertical portion of said floating gate structure over said vertical channel.
Claim 3
Dependent Claim
20 words
The electronically programmable memory device of claim 2 wherein said vertical
channel is between about 20 to 200nm in depth.
Claim 4
Dependent Claim
25 words
The electronically programmable device of claim 2 wherein the angle of said
vertical channel is between 30 to 150 degrees when measured from the horizontal.
Claim 5
Dependent Claim
32 words
The electronically programmable memory device of claim 2 wherein vertical
channel under said floating gate is of N-type material, lightly doped in the range of 1E17
to 1E19 per cm 3 .
Claim 6
Dependent Claim
68 words
The electrically programmable memory device of Claim 1 wherein an extention of said
horizontal channel is covered with another control gate (not floating) ; and said vertical and
step channel are covered with a floating gate whereby said horizontal channel and the
vertical channel are electrically controlled by two separate gates to allow injecting electrons
to move straight in the direction of motion, into the vertical floating gate.
Claim 7
Dependent Claim
67 words
The single polysilicon EPROM memory cell comprising: a series of a conventional FET transistor and a floating gate device ; said floating gate device having a horizontal and vertical step channel/drain wherein
the overlapped length of step N-drain length under the floating gate is intentionally longer
than the horizontal channel region, in order to increase coupling capacitance between drain;
and said horizontal channel /drain is normally 'on'.
Claim 8
Dependent Claim
70 words
The single polysilicon EPROM memory cell comprising: a floating gate memory transistor having a horizontal and vertical step channel/drain; and an external coupling capacitor; wherein the gate of said capacitor is formed of the same conductor material as
floating gate and connected together; said horizontal channel is normally 'off'; and said floating gate memory transistor is selected by applying a voltage to the other
terminal diffusion of said coupling capacitor.
Claim 9
Dependent Claim
89 words
The single polysilicon EPROM memory cell comprising: a floating gate memory transistor having a horizontal and vertical step channel/drain; and a coupling capacitor; wherein the floating gate of said transistor is connected to said coupling capacitor,
wherein the overlapped length of step N-drain length under the floating gate can be small,
but the coupling capacitor is at least larger than said floating gate transistor area to increase
the coupling ratio; said horizontal channel is normally 'off', said memory transistor is
selected by applying a voltage across the coupling capacitor.
Claim 10
Dependent Claim
60 words
The EPROM memory cell of Claim 9 wherein reliable erase and program operations is
performed at the same side of said step junction in said floating gate memory transistor with
a step channel/drain structure, provided by a deeper N-drain junction than that for source
and lighter doping to withstand high voltage for tunneling from the floating gate to N-drain
diffusion.
Claim 11
Dependent Claim
83 words
A double polysilicon stack EPROM memory cell comprising: a floating stack gate memory transistor with source, drain and channel and having a
horizontal and vertical step channel/drain structure that provides efficient electron injection
from the channel to said floating gate; and means for reliably erasing of said memory cell at the said horizontal and vertical step
junction provided by a deeper N-drain junction than that for source and lighter doping to
withstand high voltage for tunneling from the floating gate to N-drain diffusion.
Claim 12
Dependent Claim
85 words
A double polysilicon split gate EPROM memory cell comprising: a floating split gate memory transistor with source, drain and channel and having a
horizontal and vertical step channel/drain structure that provides efficient electron injection
from the channel to said floating gate; and means for reliably erasing of said memory cell at the said horizontal and vertical step
junction provided by a deeper N-drain junction than that for source and lighter doping to
withstand a high voltage for tunneling from the floating gate to N-drain diffusion.
Claim 13
Dependent Claim
74 words
A double polysilicon gate EPROM memory cell comprising: a double polysilicon floating gate transistor having a horizontal and vertical step
channel/drain; structure having efficient electron injection from the channel to said floating gate; a control gate; the length of overlapped floating gate over N-drain diffusion is adjusted to be longer
than horizontal channel length; and means are provided to erase said memory cell by tunneling charge from said floating
gate to said control gate.
Claim 14
Dependent Claim
35 words
The single polysilicon EPROM memory cell of Claim 9 wherein means are provided for
selected word line erase for small erase block size and extended endurance by minimizing
unnecessary program/erase cycles in floating gate transistors.
Claim 15
Dependent Claim
45 words
The double polysilicon stack EPROM memory cell of Claim 11 wherein means are
provided for erase operations by adjusting the length of overlapped floating gate over N-drain
diffusion longer than the horizontal channel length and with said drain junction as
shallow as said source junction.
Claim 16
Dependent Claim
46 words
The double polysilicon split gate EPROM memory cell of Claim 12 wherein means are
provided for erase operations by adjusting the length of overlapped floating gate over N-drain
diffusion longer than the horizontal channel length and with said drain junction as
shallow as said source junction.
Claim 17
Dependent Claim
80 words
A non-volatile RAM combining the operating features of low voltage programming and
polysilicon to polysilicon erase comprising: a substrate having source and drain regions with a channel therebetween; a floating gate structure over portions of said source and drain regions and said
channel, which structure includes a dielectric layer and a conductor layer thereover; said channel under said floating gate having both horizontal and vertical components;
and a word-line select gate located over a portion of said horizontal channel component.
Claim 18
Dependent Claim
23 words
The non-volatile RAM of Claim 17 wherein there is provided means for low voltage
programming and means for polysilicon to polysilicon erase operation.
Claim 19
Dependent Claim
116 words
A triple polysilicon electrically programmable memory device which has greater
efficiency of electron injection from the channel to the floating gate comprising: a substrate having source and drain regions with a channel therebetween; a vertically stacked polysilicon floating gate structure over portions of said source
and drain regions and said channel, which structure includes a dielectric layer and a
conductor layer thereover; said channel under said floating gate having both horizontal and vertical gate
components; and said vertical stacked floating gate structure is in series with a horizontal FET device
having a separated polysilicon gate, wherein electrons are accelerated in the horizontal
channel and injected into the vertical floating gate, utilizing the said electron injection
mechanism.
Claim 20
Dependent Claim
49 words
The triple polysilicon electrically programmable memory device of Claim 19 wherein
there is provided and extension of said horizontal polysilicon gate over said floating gate
and whereby electrons are stored on the floating gate are erased and removed by tunneling
from the floating gate to the horizontal polysilicon gate.
Claim 21
Independent Claim
74 words
A method for fabricating an electrically programmable memory device which has
efficiency of electron injection from the channel to floating gate comprising: providing a substrate having source and drain regions with a channel therebetween; providing a floating gate structure over portions of said source and drain regions and
said channel, which structure includes a dielectric layer and a conductor layer thereover; and said channel under said floating gate having both horizontal and vertical components.
Claim 22
Dependent Claim
83 words
The method for fabricating an electrically programmable memory device of Claim 21
wherein said horizontal and vertical components are a horizontal channel and a vertical
channel, and the said vertical channel is adjacent to said drain region and said horizontal
channel is adjacent to said source region which device provides in operation accelerated
electrons in the horizontal channel are injected straight in the direction of momentum into
the vertical channel and the vertical portion of said floating gate structure over said vertical
channel.
Claim 23
Dependent Claim
23 words
The electrically programmable memory method of Claim 22 said vertical channel is
channel is 30 to 150 degrees when measured from the horizontal.
Claim 24
Dependent Claim
33 words
The electrically programmable memory method of Claim 23 wherein said vertical
channel is formed by etching in the early stages of a field effect device fabrication.
between 20 to 100 nm in depth.
Claim 25
Dependent Claim
33 words
The electrically programmable memory method of Claim 23 wherein said vertical
channel is formed by etching in the early stages of a field effect device fabrication.
between 20 to 300 nm in depth.
Claim 26
Dependent Claim
50 words
The electrically programmable memory method of Claim 25 wherein after forming said
vertical channel and using the same mask to define the vertical channel step; a ion from the
group consisting of phosphorus, arsenic, and antimony is implant to form the N-drain self
aligned to the vertical channel step region.
Claim 27
Dependent Claim
39 words
The method of Claim 26 wherein said floating gate is formed over said vertical channel
step by forming a tunnel silicon oxide upon said channel and forming a first polysilicon
layer thereover and patterning to form said floating gate.
Claim 28
Dependent Claim
13 words
The method of Claim 27 wherein a stack gate memory cell is formed.
Claim 29
Dependent Claim
13 words
The method of claim 27 wherein a split gate memory cell is formed.
Claim 30
Dependent Claim
39 words
The method of Claim 26 wherein a control gate is formed over said floating gate by
depositing a composite dielectric layer over said first polysilicon layer and a second
polysilicon layer thereover and patterning to form said control gate.
Claim 31
Independent Claim
148 words
A method for fabricating an electrically programmable memory device which has greater
efficiency of electron injection from the channel to the floating gate comprising: providing a semiconductor substrate having isolated surface regions therein; providing source and drain regions with a channel therebetween within at least one of
said isolated regions; forming a vertical step within at least one of said isolated regions having said source
and drain regions by etching into said substrate with its location between said souree and
drain and to a desired depth; implanting to form an N- region over at least vertical step and in contact with either
of said source and drain regions; forming a floating gate structure over portions of said source and drain regions and
said channel, which structure includes a dielectric layer and a conductor layer thereover; and said channel under said floating gate having both horizontal and vertical components.
Claim 32
Dependent Claim
41 words
The method of Claim 31 wherein a control gate is formed over said floating gate by
forming a composite dielectric layer over said floating gate; forming a polysilicon layer
thereover and patterning said polysilicon layer to define the said control gate.
Claim 33
Dependent Claim
83 words
The method for fabricating an electrically programmable memory device of Claim 31
wherein said horizontal and vertical components are a horizontal channel and a vertical
channel, and the said vertical channel is adjacent to said drain region and said horizontal
channel is adjacent to said source region which device provides in operation accelerated
electrons in the horizontal channel are injected straight in the direction of momentum into
the vertical channel and the vertical portion of said floating gate structure over said vertical
channel.
Claim 34
Dependent Claim
19 words
The electrically programmable memory method of Claim 31 said vertical channel is
between 20 to 300 nm in depth.
Claim 35
Dependent Claim
24 words
The electrically programmable memory method of Claim 31 the angle of said vertical
channel is 30 to 150 degrees when measured from the horizontal.
Claim 36
Dependent Claim
25 words
The electrically programmable memory method of Claim 31 wherein after forming said
vertical channel and using the same mask to define the vertical channel step.
Claim 37
Dependent Claim
52 words
The method of Claim 31 wherein said floating gate is formed over said vertical channel
step by wherein said dielectric layer is made by forming a tunnel silicon oxide upon said
channel and Said conductive layer is formed by forming a first polysilicon layer thereover
and patterning to form said floating gate.
Claim 38
Dependent Claim
13 words
The method of Claim 31 wherein a stack gate memory cell is formed.
Claim 39
Dependent Claim
13 words
The method of claim 31 wherein a split gate memory cell is formed.
Claim 40
Independent Claim
179 words
A method for fabricating an electrically programmable memory device which has greater
efficiency of electron injection from the channel to the floating gate comprising: providing a semiconductor substrate having isolated surface regions therein; forming a word line gate structure within at least one of said regions; forming a source region adjacent to a word line gate structure; forming an N- drain region adjacent to said d word line gate structure but spaced
from said source region; forming a vertical step within said at least one of said isolated regions having said N- drain region by etching into said substrate with its location between said source and drain
and to a desired depth; implanting to form a highly doped drain region within said an N- drain region; forming a contact to said source region to be a word line contact; forming a floating gate structure over portions of said source and drain regions and
said channel, which structure includes a dielectric layer and a conductor layer thereover; and said channel under said floating gate having both horizontal and vertical components.
Claim 41
Independent Claim
221 words
A method for fabricating an electrically programmable memory device which has greater
efficiency of electron injection from the channel to the floating gate comprising: providing a semiconductor substrate having isolated surface regions therein; providing source and drain regions with a channel therebetween within at least one of
said isolated regions; said source and drain regions are at a level below the surface of said isolated regions; forming a vertical step within and trench at least one of said isolated regions having
said source and drain regions by etching into said substrate with its location between said
source and drain and to a depth of more than 300nm; implanting to form an N- region over at least vertical step and in contact with said
drain region; forming a floating gate structure over portions of said source and drain regions and
said channel, which structure includes a dielectric layer and a conductor layer thereover; said dielectric layer is formed on said step and said trench and said conductor layer is
polysilicon and is deposited over said dielectric layer within said trench and without of said
trench; said polysilicon layer is planarized to leave only that portion of said layer that is
within said trench to complete said floating gate structure; and said channel under said floating gate having both horizontal and vertical components.
Claim 42
Dependent Claim
23 words
The electrically programmable memory method of Claim 41 said vertical channel is
channel is 30 to 150 degrees when measured from the horizontal.
Claim 43
Dependent Claim
25 words
The electrically programmable memory method of Claim 41 wherein said vertical
channel is formed by etching to a depth of between 100 to 300 nm.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.