Voltage differential sensing circuit and methods of using same

Claim 2

A random access memory circuit comprising: a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array, comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter for receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.

Claim 3

The random access memory circuit according to claim 1 , wherein said data driver circuit comprises: a PMOS transistor having a gate coupled to said second timing signal; and an NMOS transistor coupled to said PMOS transistor and having a gate coupled to said third timing signal.

Claim 4

The random access memory circuit according to claim 2 , wherein said PMOS transistor comprises a pull up transistor and wherein said NMOS transistor comprises a pull down transistor.

Claim 5

A semiconductor chip on which is fabricated a random access memory circuit comprising: a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an activating enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line, comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.

Claim 6

A semiconductor chip on which is fabricated a random access memory circuit comprising: a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an activating enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line, comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.

Claim 7

The semiconductor chip according to claim 4 , wherein said data driver circuit comprises: a PMOS transistor with a gate coupled to said second timing signal; and an NMOS transistor coupled to said PMOS transistor and with a gate coupled to said third timing signal.

Claim 8

The semiconductor chip according to claim 5 , wherein said PMOS transistor comprises a pull up transistor and said NMOS transistor comprises a pull down transistor.

Claim 9

A computer system comprising: a processor; an input device coupled to said processor; an output device coupled to said processor; and a memory device coupled to said processor comprising: a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an activating enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line, comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter for receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.

Claim 10

A computer system comprising: a processor; an input device coupled to said processor; an output device coupled to said processor; and a memory device coupled to said processor comprising: a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an activating enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line, comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter for receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.

Claim 11

The computer system according to claim 7 , wherein said data driver circuit comprises: a PMOS transistor with a gate coupled to said second timing signal; and an NMOS transistor coupled to said PMOS transistor and with a gate coupled to said third timing signal.

Claim 12

The computer system according to claim 8 , wherein said PMOS transistor comprises a pull up transistor and said NMOS transistor comprises a pull down transistor.

Claim 13

A semiconductor wafer comprising: a semiconductor wafer; and a plurality of memory devices fabricated on said semiconductor wafer, wherein each of said memory devices comprises: a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an activating enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line, comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter for receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.

Claim 14

A semiconductor wafer comprising: a semiconductor wafer; and a plurality of memory devices fabricated on said semiconductor wafer, wherein each of said memory devices comprises: a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an activating enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line, comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter for receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.

Claim 15

The semiconductor wafer of claim 10 , wherein said data driver circuit comprises: a PMOS transistor with a gate coupled to said second timing signal; and an NMOS transistor coupled to said PMOS transistor and with a gate coupled to said third timing signal.

Claim 16

A memory module comprising: a substrate for mounting integrated circuits; and a plurality of memory devices each configured as an integrated circuit and mounted to said substrate, each of said plurality of memory devices comprising: a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an activating enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line, comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter for receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.

Claim 17

A memory module comprising: a substrate for mounting integrated circuits; and a plurality of memory devices each configured as an integrated circuit and mounted to said substrate, each of said plurality of memory devices comprising: a read/write controller; a row decoder coupled to said read/write controller; a column decoder coupled to said read/write controller; a memory array coupled to said row decoder and said column decoder; and a sense amplifier coupled to said read/write controller and said memory array comprising: a sensing circuit comprising: a pair of complementary data signal lines; an enable line for receiving an activating enable signal from said read/write controller; a helper flip-flop coupled to said pair of complementary data signal lines and said enable line; a transition logic circuit coupled to said helper flip-flop and said enable line, comprising: a first NAND gate having a first input from said enable line and a second input from a latched data signal for outputting a first timing signal; a second NAND gate having a first input from said enable line and a second input from a latched complementary data signal for balancing said transition logic circuit; a third NAND gate having a first input from said enable line and a second input from said first timing signal for outputting a second timing signal; and an inverter for receiving said first timing signal and outputting a third timing signal; and a data driver circuit coupled to said transition logic circuit for outputting a signal analogous to a signal presented on said pair of complementary data signal lines.

Claim 18

The memory module of claim 12 , wherein said data driver circuit comprises: a PMOS transistor with a gate coupled to said second timing signal; and an NMOS transistor coupled to said PMOS transistor and with a gate coupled to said third timing signal.

Claim 19

The memory module of claim 12 , wherein each of said plurality of memory device is a Dynamic Random Access Memory (DRAM).

Claim 20

The memory module of claim 12 , wherein each of said plurality of memory device is a Synchronous Graphics Random Access Memory (SGRAM).

Claim 21

The memory module of claim 12 , wherein each of said plurality of memory device is a Static Random Access Memory (SRAM).