Data output buffer

Claim 2

A semiconductor chip, comprising: a logic circuit providing a control signal; and an output circuit, responsive to the control signal, including an output terminal, a high-level circuit having an input and arranged to bias the output terminal toward a high-level reference voltage, a low-level circuit for biasing the output terminal toward a low-level reference voltage, and a disable circuit coupled to the input of the high-level circuit and responsive to a low-level signal at the output terminal, the low-level signal being less than the low-level reference voltage, and the disable circuit responding to the low-level signal by disabling the high-level circuit and causing current flow therethrough to be interrupted.

Claim 3

A semiconductor circuit device, according to claim 1, further including a voltage-doubling circuit for activating the high-level circuit.

Claim 4

A semiconductor circuit device, according to claim 1, wherein the disable circuit includes a first switch circuit coupled between the input of the high-level circuit and the output terminal and a second switch circuit arranged and constructed to reduce current flowing to the high-level circuit.

Claim 5

A semiconductor circuit device, according to claim 3, wherein the first and second switch circuits are implemented using transistors with respective switching functions at least partly controlled by the low-level signal.

Claim 6

A semiconductor circuit device, according to claim 4, wherein the transistors provide at least one drive current path to the output terminal.

Claim 7

A semiconductor circuit device, according to claim 1, wherein the logic circuit generates an enable signal to control the control signal between an operative mode and an inoperative mode.

Claim 8

A semiconductor circuit device, according to claim 1, wherein the high-level circuit further includes a pull-up circuit for biasing the output terminal in response to the control signal.

Claim 9

A semiconductor circuit device, according to claim 7, wherein the disable circuit includes an N-channel transistor, a P-channel transistor, and a contention node arranged in a current path joining the N-channel and P-channel transistors, wherein the N-channel transistor responds to the low-level signal by overpowering the P-channel transistor and setting the contention node to a voltage level to disable the pull-up circuit.

Claim 10

For use in a semiconductor circuit device, an output buffer responsive to a control signal generated in the semiconductor circuit device, the output buffer comprising: a power supply signal providing at least one voltage level with respect to common; an output terminal; a pull-up node; a circuit responding to the control signal by providing a control voltage on the pull-up node; a pull-up circuit, responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal; a bias circuit, responsive to a voltage level on the output terminal being at a level substantially below common, constructed and arranged to bias the pull-up node downwardly and away from the voltage level provided by the power supply signal; a disable circuit, responsive to the voltage level on the output terminal being at a level substantially below common, constructed and arranged to disable the circuit providing the control voltage on the pull-up node.

Claim 11

For use in a semiconductor circuit device, an output buffer responsive to a control signal generated in the semiconductor circuit device, the output buffer comprising: a power supply signal providing at least one voltage level with respect to common; an output terminal; a pull-up node; a circuit responding to the control signal by providing a control voltage on the pull-up node; a pull-up circuit, responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal; a bias circuit, responsive to a voltage level on the output terminal being at a level substantially below common, constructed and arranged to bias the pull-up node downwardly and away from the voltage level provided by the power supply signal; a disable circuit, responsive to the voltage level on the output terminal being at a level substantially below common, constructed and arranged to disable the circuit providing the control voltage on the pull-up node.

Claim 12

An output buffer, according to claim 9, wherein the disable circuit includes at least a portion of the bias circuit.

Claim 13

An output buffer, according to claim 9, wherein the level substantially below common is about equal to the voltage threshold necessary to activate an N-channel transistor.

Claim 14

An output buffer, according to claim 11, wherein common corresponds to 0 volts.

Claim 15

An output buffer, according to claim 12, wherein the power supply signal is greater than about 3 volts.

Claim 16

An output buffer, according to claim 13, further including a level adjust circuit providing a pumped power supply signal for providing power to the pull-up circuit.

Claim 17

An output buffer, according to claim 9, wherein the disable circuit includes an N-channel transistor, a P-channel transistor and a contention node arranged in a current path joining the N-channel and P-channel transistors.

Claim 18

An output buffer, according to claim 15, wherein the N-channel transistor overpowers the P-channel transistor and sets the contention node to a voltage level to disable the circuit providing the control voltage.

Claim 19

An output buffer, according to claim 16, wherein the drive of the N-channel transistor is at least an order of magnitude greater than the drive of the P-channel transistor.

Claim 20

For use in a semiconductor circuit device, a tri-state output buffer responsive to a control signal generated in the semiconductor circuit device, the output buffer comprising: a power supply signal providing at least one voltage level with respect to common; an output terminal; a pull-up node; a pull-down node; a first circuit responding to the control signal by providing a first control voltage on the pull-up node; a second circuit responding to the control signal by providing a second control voltage on the pull-down node; a pull-up transistor, responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal; a pull-down transistor, responsive to the voltage on the pull-down node and coupled between common and the output terminal; a bias circuit, responsive to a voltage level on the output terminal being at a level substantially below common, constructed and arranged to bias the pull-up node downwardly and away from the voltage level provided by the power supply signal; and a disable circuit, responsive to the voltage level on the output terminal being at a level substantially below common, constructed and arranged to disable the circuit providing the control voltage on the pull-up node; wherein the pull-up transistor provides a high-level signal at the output terminal, the pull-down transistor provides a low-level signal at the output terminal, and the bias circuit in combination with the disable circuit respond to the voltage level on the output terminal being at a level substantially below common by preventing current flow from the power supply signal to the output terminal.

Claim 21

For use in a semiconductor circuit device, a tri-state output buffer responsive to a control signal generated in the semiconductor circuit device, the output buffer comprising: a power supply signal providing at least one voltage level with respect to common; an output terminal; a pull-up node; a pull-down node; a first circuit responding to the control signal by providing a first control voltage on the pull-up node; a second circuit responding to the control signal by providing a second control voltage on the pull-down node; a pull-up transistor, responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal; a pull-down transistor, responsive to the voltage on the pull-down node and coupled between common and the output terminal; a bias circuit, responsive to a voltage level on the output terminal being at a level substantially below common, constructed and arranged to bias the pull-up node downwardly and away from the voltage level provided by the power supply signal; and a disable circuit, responsive to the voltage level on the output terminal being at a level substantially below common, constructed and arranged to disable the circuit providing the control voltage on the pull-up node; wherein the pull-up transistor provides a high-level signal at the output terminal, the pull-down transistor provides a low-level signal at the output terminal, and the bias circuit in combination with the disable circuit respond to the voltage level on the output terminal being at a level substantially below common by preventing current flow from the power supply signal to the output terminal.

Claim 22

An output buffer, according to claim 18, further including a contention node which is biased by the disable circuit to substantially offset the control voltage on the pull-up node.

Claim 23

An output buffer, according to claim 18, wherein the disable circuit includes at least a portion of the bias circuit.