Semiconductor device isolation structure and method of forming

Claim 1

A method for isolating semiconductor devices, the method comprising: forming a first oxide layer outwardly from a semiconductor substrate; forming a first nitride layer outwardly from the first oxide layer; removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region; forming a second oxide layer in the trench isolation region; forming a spin-on-glass region in the trench isolation region; annealing the spin-on-glass region; removing a portion of the spin-on-glass region to expose a shallow trench isolation region; and forming a third oxide layer in the shallow trench isolation region.

Claim 2

A method for isolating semiconductor devices, the method comprising: forming a first oxide layer outwardly from a semiconductor substrate; forming a first nitride layer outwardly from the first oxide layer; removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region; forming a second oxide layer in the trench isolation region; forming a spin-on-glass region in the trench isolation region; annealing the spin-on-glass region; removing a portion of the spin-on-glass region to expose a shallow trench isolation region; and forming a third oxide layer in the shallow trench isolation region.

Claim 10

A method for isolating semiconductor devices, the method comprising: forming a first oxide layer outwardly from a semiconductor substrate; forming a first nitride layer outwardly from the first oxide layer; removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region having a depth between approximately 0.7 microns and 1.3 microns and a width between approximately 0.1 microns and 0.13 microns; forming a second oxide layer in the trench isolation region; forming a spin-on-glass region in the trench isolation region; annealing the spin-on-glass region at a temperature between approximately 300° C. and 400° C. for a time period between approximately 15 and 30 minutes, and then annealing the spin-on-glass region at a temperature between approximately 900° C. and 1000° C. for a time period between approximately 5 and 10 minutes; removing a portion of the spin-on-glass region to expose a shallow trench isolation region having a depth between approximately 2000 Å and 2700 Å; forming a third oxide layer in the shallow trench isolation region; and polishing the third oxide layer by utilizing a chemical mechanical polishing technique.

Claim 11

A method for isolating semiconductor devices, the method comprising: forming a first oxide layer outwardly from a semiconductor substrate; forming a first nitride layer outwardly from the first oxide layer; removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region having a depth between approximately 0.7 microns and 1.3 microns and a width between approximately 0.1 microns and 0.13 microns; forming a second oxide layer in the trench isolation region; forming a spin-on-glass region in the trench isolation region; annealing the spin-on-glass region at a temperature between approximately 300° C. and 400° C. for a time period between approximately 15 and 30 minutes, and then annealing the spin-on-glass region at a temperature between approximately 900° C. and 1000° C. for a time period between approximately 5 and 10 minutes; removing a portion of the spin-on-glass region to expose a shallow trench isolation region having a depth between approximately 2000 Å and 2700 Å; forming a third oxide layer in the shallow trench isolation region; and polishing the third oxide layer by utilizing a chemical mechanical polishing technique.